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公开(公告)号：US10459724B2
公开(公告)日：2019-10-29
申请号：US16037767
申请日：2018-07-17
Inventor： Hao Yu , Yuhao Wang , Junfeng Zhao , Wei Yang , Shihai Xiao , Leibin Ni
IPC: G06F9/30 , G06F17/16 , G11C13/00 , G11C7/10 , G11C5/02 , G06F7/00 , G06F13/00 , G06N3/063 , G06J1/00
Abstract: Embodiments of the present disclosure provide a memory device. The memory device includes an RRAM crossbar array that is configured to perform a logic operation, and resistance values of resistors in the RRAM crossbar array are all set to Ron or Roff to indicate a value 1 or 0. Based on the foregoing setting, an operation is implemented using the RRAM crossbar array, so that reliability of a logic operation of the RRAM crossbar array can be improved.
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公开(公告)号：US20180321942A1
公开(公告)日：2018-11-08
申请号：US16037767
申请日：2018-07-17
Inventor： Hao Yu , Yuhao Wang , Junfeng Zhao , Wei Yang , Shihai Xiao , Leibin Ni
CPC classification number: G06F9/30036 , G06F7/00 , G06F9/3001 , G06F9/30025 , G06F13/00 , G06F17/16 , G06J1/00 , G06N3/0635 , G11C5/02 , G11C7/1006 , G11C13/0023 , G11C13/003 , G11C13/004 , G11C2213/71 , G11C2213/77
Abstract: Embodiments of the present disclosure provide a memory device. The memory device includes an RRAM crossbar array that is configured to perform a logic operation, and resistance values of resistors in the RRAM crossbar array are all set to Ron or Roff to indicate a value 1 or 0. Based on the foregoing setting, an operation is implemented using the RRAM crossbar array, so that reliability of a logic operation of the RRAM crossbar array can be improved.
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公开(公告)号：US10346701B2
公开(公告)日：2019-07-09
申请号：US15695681
申请日：2017-09-05
Inventor： Hao Yu , Yuhao Wang , Leibin Ni , Wei Yang , Junfeng Zhao , Shihai Xiao
Abstract: An image recognition accelerator, a terminal device, and an image recognition method are provided. The image recognition accelerator includes a dimensionality-reduction processing module, an NVM, and an image matching module. The dimensionality-reduction processing module first reduces a dimensionality of first image data. The NVM writes, into a first storage area of the NVM according to a specified first current I, ω low-order bits of each numeric value of the first image data on which dimensionality reduction has been performed, and writes, into a second storage area of the NVM according to a specified second current, (N−ω) high-order bits of each numeric value of the first image data on which dimensionality reduction has been performed. The image matching module determines whether an image library stored in the NVM includes image data matching the first image data on which dimensionality reduction has been performed.
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公开(公告)号：US20180012095A1
公开(公告)日：2018-01-11
申请号：US15695681
申请日：2017-09-05
Inventor： Hao Yu , Yuhao Wang , Leibin Ni , Wei Yang , Junfeng Zhao , Shihai Xiao
CPC classification number: G06K9/00973 , G06K9/00 , G06K9/6201
Abstract: An image recognition accelerator, a terminal device, and an image recognition method are provided. The image recognition accelerator includes a dimensionality-reduction processing module, an NVM, and an image matching module. The dimensionality-reduction processing module first reduces a dimensionality of first image data. The NVM writes, into a first storage area of the NVM according to a specified first current I, ω low-order bits of each numeric value of the first image data on which dimensionality reduction has been performed, and writes, into a second storage area of the NVM according to a specified second current, (N−ω) high-order bits of each numeric value of the first image data on which dimensionality reduction has been performed. The image matching module determines whether an image library stored in the NVM includes image data matching the first image data on which dimensionality reduction has been performed.
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公开(公告)号：US20150344519A1
公开(公告)日：2015-12-03
申请号：US14376675
申请日：2013-02-06
Applicant: NANYANG TECHNOLOGICAL UNIVERSITY
Inventor： Chuan Fa Liu , Junfeng Zhao
Abstract: The invention relates to the synthesis of peptides, proteins and related bioconjugates, and in particular, to such synthesis using a peptide ligation method whereby a C-terminal salicylaldehyde ester peptide is reacted with an aminoacyl-N-hydroxl peptide. The invention also relates to the synthesis of cyclic peptides, including serinyl- or threonyl-containing cyclic peptides. The invention further relates to a solid phase synthesis of C-terminal salicylaldehyde ester peptides.
Abstract translation: 本发明涉及肽，蛋白质和相关生物缀合物的合成，特别涉及使用C-末端水杨醛酯肽与氨基酰基-N-羟基肽反应的肽连接方法的这种合成。 本发明还涉及环肽的合成，包括含有丝氨酰基或苏氨酰的环肽。 本发明还涉及C-末端水杨醛酯肽的固相合成。
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Patent Agency Ranking
公开(公告)号：US09453044B2
公开(公告)日：2016-09-27
申请号：US14376675
申请日：2013-02-06
Applicant: NANYANG TECHNOLOGICAL UNIVERSITY
Inventor： Chuan Fa Liu , Junfeng Zhao
Abstract: The invention relates to the synthesis of peptides, proteins and related bioconjugates, and in particular, to such synthesis using a peptide ligation method whereby a C-terminal salicylaldehyde ester peptide is reacted with an aminoacyl-N-hydroxl peptide. The invention also relates to the synthesis of cyclic peptides, including serinyl- or threonyl-containing cyclic peptides. The invention further relates to a solid phase synthesis of C-terminal salicylaldehyde ester peptides.
Abstract translation: 本发明涉及肽，蛋白质和相关生物缀合物的合成，特别涉及使用C-末端水杨醛酯肽与氨基酰基-N-羟基肽反应的肽连接方法的这种合成。 本发明还涉及环肽的合成，包括含有丝氨酰基或苏氨酰的环肽。 本发明还涉及C-末端水杨醛酯肽的固相合成。
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公开(公告)号：US20240427730A1
公开(公告)日：2024-12-26
申请号：US18830297
申请日：2024-09-10
Applicant: HUAWEI TECHNOLOGIES CO., LTD. , Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences
Inventor： Xiaogang Chen , Wentao Tang , Shunfen Li , Xi Li , Junfeng Zhao , Xiaolong Shen
IPC: G06F16/11 , G06F16/18 , G06F16/188
Abstract: A process management method and a related electronic device are provided. According to the method, process data in a volatile memory can be migrated to a non-volatile memory in real time in a running process of a system. When the system is asleep, data in a memory does not need to be packaged and backed up. When the system is woken up or restarted, data does not need to be parsed and reconstructed, to implement quick sleeping and waking up of the system. In addition, even if the system is restarted due to an unexpected power failure, a loss of key data in the memory can be avoided, and a speed of waking up or restarting the system can also be improved.
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公开(公告)号：US10976800B2
公开(公告)日：2021-04-13
申请号：US15882612
申请日：2018-01-29
Applicant: Huawei Technologies Co., Ltd. , Fudan University
Inventor： RenHua Yang , Junfeng Zhao , Wei Yang , Shihai Xiao , Yinyin Lin , Yi Wei
IPC: G06F1/3287 , G06F3/06 , G06F1/3228 , G06F1/3234 , G06F9/4401 , G06F12/0868
Abstract: An electronic device includes a processor, a volatile memory, and a non-volatile memory. The non-volatile memory stores a first operating system, and the electronic device works in a first working mode and a second working mode. When the electronic device is in the first working mode, a second operating system is run in the volatile memory. When the processor detects that the electronic device reaches a preset condition for entering the second working mode, the non-volatile memory is enabled, and non-system data in the volatile memory is moved to the non-volatile memory. The non-system data does not include the second operating system. After the movement of the non-system data is completed, the volatile memory is disabled, and the first operating system is run in the non-volatile memory, so that the electronic device enters the second working mode.
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公开(公告)号：US10069189B2
公开(公告)日：2018-09-04
申请号：US15276207
申请日：2016-09-26
Applicant: Huawei Technologies Co., Ltd.
Inventor： Shaojie Chen , Zhulin Wei , Junfeng Zhao , Rui He , Xiaowen Dong , Peng Lin , Wei Yang
Abstract: A cabinet server and a data center where the cabinet server includes multiple function node layers vertically arranged to form a server core and multiple intra-cabinet antennas vertically arranged and disposed at one side of the server core, an intra-cabinet antenna is wirelessly connected to adjacent intra-cabinet antennas. A transmission path is formed of the vertically arranged intra-cabinet antennas when a radio signal is transmitted within the cabinet server. Since the intra-cabinet antennas are disposed at the side of the server core, electromagnetic radiation generated by the radio signal in a transmission process has a relatively small effect on the function nodes, thereby reducing the effect of the electromagnetic radiation on various electronic devices in the function nodes, improving service lives of the electronic devices, and improving transmission quality of the radio signal.
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公开(公告)号：US09899084B2
公开(公告)日：2018-02-20
申请号：US15412509
申请日：2017-01-23
Applicant: Huawei Technologies Co., Ltd.
Inventor： Zhen Li , Qiang He , Xiangshui Miao , Ronggang Xu , Junfeng Zhao , Shujie Zhang
CPC classification number: G11C13/0069 , G11C11/5678 , G11C13/0004 , G11C13/0097 , G11C2013/0092 , G11C2213/79
Abstract: A data storage method applying to the phase change memory and a phase change memory are provided. After obtaining to-be-stored data, the phase change memory generates an erase pulse signal and a write pulse signal according to the to-be-stored data. The to-be-stored data is multi-bit data. The write pulse signal is a signal including at least two consecutive pulses with a same amplitude. The amplitude of the at least two consecutive pulses is a value determined according to the to-be-stored data. Then, the phase change memory applies the erase pulse signal to a storage unit of the phase change memory to allow the storage unit to switch to a crystalline state. Further, the write pulse signal is applied to the storage unit to allow the storage unit to switch to an amorphous state corresponding to a first resistance value, where the amorphous state represents the to-be-stored data.
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