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公开(公告)号：US10459724B2
公开(公告)日：2019-10-29
申请号：US16037767
申请日：2018-07-17
Inventor： Hao Yu , Yuhao Wang , Junfeng Zhao , Wei Yang , Shihai Xiao , Leibin Ni
IPC: G06F9/30 , G06F17/16 , G11C13/00 , G11C7/10 , G11C5/02 , G06F7/00 , G06F13/00 , G06N3/063 , G06J1/00
Abstract: Embodiments of the present disclosure provide a memory device. The memory device includes an RRAM crossbar array that is configured to perform a logic operation, and resistance values of resistors in the RRAM crossbar array are all set to Ron or Roff to indicate a value 1 or 0. Based on the foregoing setting, an operation is implemented using the RRAM crossbar array, so that reliability of a logic operation of the RRAM crossbar array can be improved.
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公开(公告)号：US10346701B2
公开(公告)日：2019-07-09
申请号：US15695681
申请日：2017-09-05
Inventor： Hao Yu , Yuhao Wang , Leibin Ni , Wei Yang , Junfeng Zhao , Shihai Xiao
Abstract: An image recognition accelerator, a terminal device, and an image recognition method are provided. The image recognition accelerator includes a dimensionality-reduction processing module, an NVM, and an image matching module. The dimensionality-reduction processing module first reduces a dimensionality of first image data. The NVM writes, into a first storage area of the NVM according to a specified first current I, ω low-order bits of each numeric value of the first image data on which dimensionality reduction has been performed, and writes, into a second storage area of the NVM according to a specified second current, (N−ω) high-order bits of each numeric value of the first image data on which dimensionality reduction has been performed. The image matching module determines whether an image library stored in the NVM includes image data matching the first image data on which dimensionality reduction has been performed.
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公开(公告)号：US20180012095A1
公开(公告)日：2018-01-11
申请号：US15695681
申请日：2017-09-05
Inventor： Hao Yu , Yuhao Wang , Leibin Ni , Wei Yang , Junfeng Zhao , Shihai Xiao
CPC classification number: G06K9/00973 , G06K9/00 , G06K9/6201
Abstract: An image recognition accelerator, a terminal device, and an image recognition method are provided. The image recognition accelerator includes a dimensionality-reduction processing module, an NVM, and an image matching module. The dimensionality-reduction processing module first reduces a dimensionality of first image data. The NVM writes, into a first storage area of the NVM according to a specified first current I, ω low-order bits of each numeric value of the first image data on which dimensionality reduction has been performed, and writes, into a second storage area of the NVM according to a specified second current, (N−ω) high-order bits of each numeric value of the first image data on which dimensionality reduction has been performed. The image matching module determines whether an image library stored in the NVM includes image data matching the first image data on which dimensionality reduction has been performed.
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公开(公告)号：US20180321942A1
公开(公告)日：2018-11-08
申请号：US16037767
申请日：2018-07-17
Inventor： Hao Yu , Yuhao Wang , Junfeng Zhao , Wei Yang , Shihai Xiao , Leibin Ni
CPC classification number: G06F9/30036 , G06F7/00 , G06F9/3001 , G06F9/30025 , G06F13/00 , G06F17/16 , G06J1/00 , G06N3/0635 , G11C5/02 , G11C7/1006 , G11C13/0023 , G11C13/003 , G11C13/004 , G11C2213/71 , G11C2213/77
Abstract: Embodiments of the present disclosure provide a memory device. The memory device includes an RRAM crossbar array that is configured to perform a logic operation, and resistance values of resistors in the RRAM crossbar array are all set to Ron or Roff to indicate a value 1 or 0. Based on the foregoing setting, an operation is implemented using the RRAM crossbar array, so that reliability of a logic operation of the RRAM crossbar array can be improved.
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