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公开(公告)号：US09953796B2
公开(公告)日：2018-04-24
申请号：US15098108
申请日：2016-04-13
发明人： Biqin Huang , Christopher S. Roper , Tahir Hussain
摘要： A semiconductor power handling device, includes a cathode pillar, a gate surrounding the cathode pillar, and an anode spaced from the cathode by a nano-vacuum gap. An array of semiconductor power handling devices, each comprising a cathode pillar, a gate surrounding the cathode pillar, and an anode spaced from the cathode pillar by a nano-vacuum gap. The semiconductor power handling devices can be arranged as rows and columns and can be interconnected to meet the requirements of various applications. The array of power handling devices can be fabricated on a single substrate.
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公开(公告)号：US09662498B1
公开(公告)日：2017-05-30
申请号：US14669794
申请日：2015-03-26
申请人： HRL LABORATORIES LLC
发明人： Kyung-Ah Son , Jeong-Sun Moon , Zhiwei A. Xu , Brian N. Limketkai , Jongchan Kang , Tahir Hussain
CPC分类号： G01N33/4836 , A61B5/0478 , A61B5/6868 , A61B2562/0209 , A61B2562/028 , A61B2562/046 , A61N1/0531 , A61N1/36125 , A61N1/37229 , A61N1/3787 , C23C16/26 , C23C16/45525 , C23C16/56 , H01L21/02527 , H01L21/0262 , H01L21/042 , H01L21/044
摘要： A neuroelectric sensor and stimulator system includes a first antenna, a reader coupled to the first antenna for transmitting stimulation controls and power to a second antenna, and for receiving sensor data transmitted from the second antenna via the first antenna, and at least one neuroelectric sensor stimulator array including the second antenna, a rectifier coupled to the second antenna for extracting power transmitted from the first antenna, a controller coupled to the second antenna for decoding controls transmitted from the first antenna to the second antenna for the neuroelectric sensor stimulator array, a plurality of sensors, a multiplexer coupled to the controller and to the plurality of sensors for selecting a single sensor, and a plurality of stimulators coupled to the controller for stimulating neurons, wherein the rectifier, the controller, the plurality of sensors, the multiplexer, and the plurality of stimulators include graphene.
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公开(公告)号：US09536844B1
公开(公告)日：2017-01-03
申请号：US14678512
申请日：2015-04-03
发明人： Peter D. Brewer , Dana C. Wheeler , Tahir Hussain , Kyung-Ah Son , Hyok J. Song , Harris P. Moyer , Joseph S. Colburn , James H. Schaffner
IPC分类号： H01L27/144 , H01L23/66 , H01L23/00 , H01L23/498 , H01L29/167 , H01L29/32 , H01Q1/02 , H01Q1/14
CPC分类号： H01L23/66 , H01L23/4985 , H01L23/49866 , H01L23/49894 , H01L23/57 , H01L29/167 , H01L29/32 , H01L2223/6677 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01Q9/005 , H01L2924/00014
摘要： The disclosed antenna structures and electronic microsystems are capable of physically disappearing in a controlled, triggerable manner. Some variations provide an on-chip transient antenna comprising a semiconductor substrate containing ion-implanted hydrogen atoms and a conductor network comprising metals bridged by low-melting-temperature metals. Some variations provide an off-chip transient antenna comprising a flexible substrate containing a polymer, nanoporous silicon particles, and an oxidant for silicon, and a conductor network comprising metals bridged by low-melting-temperature metals. Other variations provide a method of introducing physical transience to a semiconductor integrated circuit, comprising thinning a substrate from the back side, implanting hydrogen ions into the thinned substrate to introduce latent structural flaws, depositing a semiconductor integrated circuit or sensor chip, and providing a controllable heating source capable of activating the latent structural flaws. These novel approaches are compatible with existing integrated circuits processing, preserve antenna performance, and use foundry-compatible techniques.
摘要翻译： 所公开的天线结构和电子微系统能够以受控的，可触发的方式物理地消失。 一些变型提供包括含有离子注入的氢原子的半导体衬底的片上瞬态天线和包含由低熔点金属桥接的金属的导体网络。 一些变型提供了包括含有聚合物，纳米多孔硅颗粒和硅氧化剂的柔性基板的片外瞬态天线，以及包含由低熔点金属桥接的金属的导体网络。 其它变型提供了一种将物理瞬态引入半导体集成电路的方法，包括从背面稀释衬底，将氢离子注入到薄化衬底中以引入潜在的结构缺陷，沉积半导体集成电路或传感器芯片，以及提供可控制的 能够激活潜在结构缺陷的加热源。 这些新颖的方法与现有的集成电路处理兼容，保留天线性能，并使用代工兼容技术。
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4.发明授权Enhancement mode normally-off gallium nitride heterostructure field effect transistor 有权增强型常闭氮化镓异质结场场效应晶体管公开(公告)号：US09190534B1
公开(公告)日：2015-11-17
申请号：US14248695
申请日：2014-04-09
发明人： Tahir Hussain , Miroslav Micovic , Wah S. Wong , Shawn D. Burnham
IPC分类号： H01L21/338 , H01L29/80 , H01L29/20 , H01L29/205
CPC分类号： H01L29/7787 , H01L29/2003 , H01L29/207 , H01L29/402 , H01L29/42316 , H01L29/66462
摘要： A method of fabricating a normally “off” GaN heterostructure field effect transistor having a source and a drain including depositing a passivation layer patterned to cover a channel region between a source and a drain, forming a first opening in the passivation layer, the first opening for defining a gate area in the channel region and the first opening having a first length dimension along a direction of current flow between the source and the drain, and implanting ions in an implant area within the gate area, wherein the implant area has a second length dimension along the direction of current flow shorter than the first length dimension.
摘要翻译： 一种制造具有源极和漏极的正常“关闭”GaN异质结构场效应晶体管的方法，包括沉积图案化以覆盖源极和漏极之间的沟道区域的钝化层，在钝化层中形成第一开口，第一开口 用于在所述沟道区域中限定栅极区域，并且所述第一开口沿着所述源极和漏极之间的电流流动的方向具有第一长度尺寸，以及将离子注入所述栅极区域内的注入区域中，其中所述植入区域具有第二 沿着电流流动方向的长度尺寸短于第一长度尺寸。
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公开(公告)号：US09087854B1
公开(公告)日：2015-07-21
申请号：US14158962
申请日：2014-01-20
IPC分类号： H01L23/60 , H01L29/66 , H01L27/06 , H01L29/778
CPC分类号： H01L29/66431 , H01L21/8252 , H01L21/8258 , H01L23/36 , H01L23/3677 , H01L27/0623 , H01L27/0688
摘要： A method of three dimensional heterogeneous integration including forming HBT devices on a first substrate, each HBT device having a collector, removing the first substrate, forming first bonding pads on each collector of the heterojunction bipolar transistor devices, forming high electron mobility transistor (HEMT) devices on a first side of a growth substrate, wherein the growth substrate comprises a thermally conductive substrate, such as SiC or diamond, forming second bonding pads on the first side of the growth substrate, aligning and bonding the first bonding pads to the second bonding pads, forming CMOS devices on a Si substrate, bonding the CMOS devices on the Si substrate to a second side of the growth substrate, and forming selectively interconnects between the HBT devices, the HEMT devices, and the CMOS devices by forming vias and first and second level metal interconnects.
摘要翻译： 一种三维非均匀集成的方法，包括在第一衬底上形成HBT器件，每个HBT器件具有集电极，去除第一衬底，在异质结双极晶体管器件的每个集电极上形成第一接合焊盘，形成高电子迁移率晶体管（HEMT） 生长衬底的第一侧上的器件，其中所述生长衬底包括诸如SiC或金刚石的导热衬底，在所述生长衬底的第一侧上形成第二接合焊盘，将所述第一接合焊盘对准和接合到所述第二接合 衬垫，在Si衬底上形成CMOS器件，将Si衬底上的CMOS器件接合到生长衬底的第二侧，以及通过形成通孔，首先形成通孔并在HBT器件，HEMT器件和CMOS器件之间选择性地形成互连 二级金属互连。
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公开(公告)号：US09880148B1
公开(公告)日：2018-01-30
申请号：US15478129
申请日：2017-04-03
发明人： Kyung-Ah Son , Jeong-Sun Moon , Zhiwei A. Xu , Brian N. Limketkai , Jongchan Kang , Tahir Hussain
IPC分类号： A61N1/00 , G01N33/483 , C23C16/455 , C23C16/56 , C23C16/26 , H01L21/04 , H01L21/02
CPC分类号： G01N33/4836 , A61B5/0478 , A61B5/6868 , A61B2562/0209 , A61B2562/028 , A61B2562/046 , A61N1/0531 , A61N1/36125 , A61N1/37229 , A61N1/3787 , C23C16/26 , C23C16/45525 , C23C16/56 , H01L21/02527 , H01L21/0262 , H01L21/042 , H01L21/044
摘要： A neuroelectric sensor and stimulator system includes a first antenna, a reader coupled to the first antenna for transmitting stimulation controls and power to a second antenna, and for receiving sensor data transmitted from the second antenna via the first antenna, and at least one neuroelectric sensor stimulator array including the second antenna, a rectifier coupled to the second antenna for extracting power transmitted from the first antenna, a controller coupled to the second antenna for decoding controls transmitted from the first antenna to the second antenna for the neuroelectric sensor stimulator array, a plurality of sensors, a multiplexer coupled to the controller and to the plurality of sensors for selecting a single sensor, and a plurality of stimulators coupled to the controller for stimulating neurons, wherein the rectifier, the controller, the plurality of sensors, the multiplexer, and the plurality of stimulators include graphene.
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公开(公告)号：US09691761B1
公开(公告)日：2017-06-27
申请号：US15335207
申请日：2016-10-26
发明人： Pamela R. Patterson , Keisuke Shinohara , Hasan Sharifi , Wonill Ha , Tahir Hussain , James Chingwei Li , Dana C. Wheeler
IPC分类号： H01L27/00 , H01L27/06 , H01L21/8258 , H01L29/165
CPC分类号： H01L27/0688 , H01L21/8252 , H01L21/8258 , H01L21/84 , H01L23/481 , H01L27/0605 , H01L27/085 , H01L27/1203 , H01L29/165 , H01L2224/32145 , H01L2224/73265 , H01L2224/97
摘要： A compound semiconductor integrated circuit comprising a first substrate; a first electronic component formed on top of said first substrate; a layer of a first dielectric material formed on top of said first substrate and including said first electronic component, said layer of a first dielectric material comprising a recess exposing a first region of said first substrate; and a layer of a second dielectric material attached to said first substrate on top of said first region of said first substrate after manufacturing of said layer of a second dielectric material, said layer of a second material comprising a second electronic component.
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公开(公告)号：US09515068B1
公开(公告)日：2016-12-06
申请号：US14014121
申请日：2013-08-29
发明人： Pamela R. Patterson , Keisuke Shinohara , Hasan Sharifi , Wonill Ha , Tahir Hussain , James Chingwei Li , Dana C. Wheeler
CPC分类号： H01L27/0688 , H01L21/8252 , H01L21/8258 , H01L21/84 , H01L23/481 , H01L27/0605 , H01L27/085 , H01L27/1203 , H01L29/165 , H01L2224/32145 , H01L2224/73265 , H01L2224/97
摘要： A compound semiconductor integrated circuit comprising a first substrate; a first electronic component formed on top of said first substrate; a layer of a first dielectric material formed on top of said first substrate and including said first electronic component, said layer of a first dielectric material comprising a recess exposing a first region of said first substrate; and a layer of a second dielectric material attached to said first substrate on top of said first region of said first substrate after manufacturing of said layer of a second dielectric material, said layer of a second material comprising a second electronic component.
摘要翻译： 一种复合半导体集成电路，包括第一衬底; 形成在所述第一基板的顶部上的第一电子部件; 形成在所述第一基板的顶部并包括所述第一电子部件的第一介电材料层，所述第一介电材料层包括露出所述第一基板的第一区域的凹部; 以及在制造所述第二介电材料层之后，在所述第一衬底的所述第一区域的顶部附着到所述第一衬底的第二电介质材料层，所述第二材料层包括第二电子部件。
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公开(公告)号：US12057429B1
公开(公告)日：2024-08-06
申请号：US17356387
申请日：2021-06-23
IPC分类号： H01L23/00
CPC分类号： H01L24/81 , H01L24/13 , H01L24/14 , H01L24/16 , H01L2224/13013 , H01L2224/13016 , H01L2224/13144 , H01L2224/13466 , H01L2224/14051 , H01L2224/16057 , H01L2224/80201 , H01L2224/80986 , H01L2224/81053 , H01L2224/81193 , H01L2224/81203 , H01L2224/81379
摘要： A method for bonding two confronting electronic devices together wherein the two electronic devices are initially temporarily coupled together using a room temperature process with a plurality of knife-edge microstructures on at least a first one of the electronic devices engaging portions of the a second one of the electronic devices. The room temperature process involves applying a relatively low compressive force or pressure between the two electronic devices compared to the forces or pressures used in convention flip-chip bonding. The first one of the electronic devices and the second one of the electronic devices also have traditional contact pads that are spaced from each other by a standoff distance when the devices are initially coupled together using the room temperature process. This allows for inspection of the two electronic devices while they are initially temporarily coupled together. In need be, the two can be separated at this stage for re-work After passing inspection, a relatively higher compressive force or pressure is applied between the two electronic devices to cause the standoff distance to decrease to zero and for the contact pads confronting each other on the confronting two electronic devices to weld thereby permanently bonding the two electronic devices together.
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公开(公告)号：US11562984B1
公开(公告)日：2023-01-24
申请号：US17070826
申请日：2020-10-14
IPC分类号： H01L25/065 , H01L23/00 , H01L25/00
摘要： A method and apparatus for laterally urging two semiconductor chips, dies or wafers into an improved state of registration with each other, the method and apparatus employing microstructures comprising: a first microstructure disposed on a first major surface of a first one of said two semiconductor chips, dies or wafers, wherein the first microstructure includes a sidewall which is tapered thereby disposing it at an acute angle compared to a perpendicular of said first major surface, and a second microstructure disposed on a first surface of a second one of said two semiconductor chips, dies or wafers, wherein the shape of the second microstructure is complementary to, and mates with or contacts, in use, the first microstructure, the second microstructure including a surface which contacts said sidewall when the first and second microstructures are mated or being mated, the sidewall of the first microstructure and the surface of the second microstructure imparting a lateral force for urging the two semiconductor chips, dies or wafers into said improved state of registration.
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