公开(公告)号：US20180225050A1

公开(公告)日：2018-08-09

申请号：US15943136

申请日：2018-04-02

Applicant: Hitachi, Ltd.

Inventor： Akifumi Suzuki ,  Takashi Tsunehiro

IPC: G06F3/06 ,  G11C29/02 ,  G11C16/34 ,  G11C16/00

CPC classification number: G06F3/0616 ,  G06F3/0629 ,  G06F3/0679 ,  G11C16/00 ,  G11C16/3431 ,  G11C16/3495 ,  G11C29/021 ,  G11C29/028

Abstract: A semiconductor storage device has a nonvolatile semiconductor memory comprised from multiple storage areas, and a controller, which is coupled to the nonvolatile semiconductor memory. The controller (A) identifies a storage area state, which is the state of a storage area, (B) decides, based on the storage area state identified in the (A), a read parameter, which is a parameter for use when reading data from a storage area with respect to a storage area of this storage area state, and (C) uses the read parameter decided in the (B) with respect to a read-target storage area and reads data from this read-target storage area.

公开(公告)号：US09933976B2

公开(公告)日：2018-04-03

申请号：US15126693

申请日：2014-04-28

Applicant: Hitachi, Ltd.

Inventor： Yoshitaka Tsujimoto ,  Satoru Watanabe ,  Yoshiki Kurokawa ,  Mitsuhiro Okada ,  Akifumi Suzuki

IPC: G06F3/06 ,  G06F11/10

CPC classification number: G06F3/0659 ,  G06F3/061 ,  G06F3/0656 ,  G06F3/0658 ,  G06F3/0688 ,  G06F11/1044 ,  G06F12/00

Abstract: A storage apparatus has a plurality of hardware engines which send and receive information to and from a controller, which, on the condition of acquiring a request command from a host, determines identifying information of the request command, executes data I/O processing to the storage device according to the request command when first identifying information has been added to the request command and when second identifying information has been added to the acquired request command, transfers the request command to the hardware engine, acquires the data requested by the hardware engine from the storage device and transfers the acquired data to the hardware engine. The hardware engine acquires and analyzes an add-on command from the host and according to the request command, requests the controller to transfer the data based on the analysis result, and thereafter executes processing to the data transferred by the controller according to the add-on command.

公开(公告)号：US09070463B2

公开(公告)日：2015-06-30

申请号：US14560313

申请日：2014-12-04

Applicant: Hitachi, Ltd.

Inventor： Akifumi Suzuki

IPC: G11C16/04 ,  G11C16/16

CPC classification number: G11C16/16 ,  G06F3/0616 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0679 ,  G06F12/0246 ,  G06F2212/7211 ,  G11C16/3431 ,  G11C16/3436

Abstract: A flash memory module may include a plurality of flash memory chips. The memory chips may include one or more blocks. Each block may be a unit of erasing data. A flash controller may be coupled to the plurality of flash memory chips. The flash controller may program data to block and erase data from a block. The flash controller may manage a recent programming time for each of the plurality of blocks. The flash controller may erase data stored in a block for which an elapsed programming time is larger than a first value.

Abstract translation: 闪存模块可以包括多个闪存芯片。 存储器芯片可以包括一个或多个块。 每个块可以是擦除数据的单元。 闪存控制器可以耦合到多个闪存芯片。 闪存控制器可以编程数据来阻止和擦除块中的数据。 闪存控制器可以管理多个块中的每一个的最近的编程时间。 闪存控制器可以擦除存储在经过编程时间大于第一值的块中的数据。

公开(公告)号：US20140189203A1

公开(公告)日：2014-07-03

申请号：US13811008

申请日：2012-12-28

Applicant: Hitachi, Ltd.

Inventor： Akifumi Suzuki ,  Junji Ogawa ,  Akira Yamamoto

IPC: G06F12/02

CPC classification number: G06F12/0246 ,  G06F12/0866 ,  G06F12/0868 ,  G06F12/0871 ,  G06F2212/222 ,  G06F2212/282 ,  G06F2212/502

Abstract: A cache memory (CM) in which data, which is accessed with respect to a storage device, is temporarily stored is coupled to a controller for accessing the storage device in accordance with an access command from a higher-level apparatus. The CM comprises a nonvolatile semi-conductor memory (NVM), and provides a logical space to the controller. The controller is configured to partition the logical space into multiple segments and to manage these segments, and to access the CM by specifying a logical address of the logical space. The CM receives the logical address-specified access, and accesses a physical area allocated to a logical area, which belongs to the specified logical address. A first management unit, which is a unit of a segment, is larger than a second management unit, which is a unit of an access performed with respect to the NVM. The capacity of the logical space is larger than the storage capacity of the NVM.

Abstract translation: 临时存储关于存储装置访问的数据的高速缓存存储器（CM）被耦合到控制器，用于根据来自上级装置的访问命令访问存储装置。 CM包括非易失性半导体存储器（NVM），并向控制器提供逻辑空间。 控制器被配置为将逻辑空间划分成多个段并且管理这些段，并且通过指定逻辑空间的逻辑地址来访问CM。 CM接收逻辑地址指定的访问，并访问分配给属于指定逻辑地址的逻辑区域的物理区域。 作为段的单位的第一管理单元大于作为相对于NVM执行的访问的单位的第二管理单元。 逻辑空间的容量大于NVM的存储容量。

公开(公告)号：US12050797B2

公开(公告)日：2024-07-30

申请号：US17878138

申请日：2022-08-01

Applicant: Hitachi, Ltd.

Inventor： Hiroaki Akutsu ,  Takahiro Naruko ,  Akifumi Suzuki

IPC: G06F3/06 ,  G06Q30/0645

CPC classification number: G06F3/0644 ,  G06F3/0605 ,  G06F3/067 ,  G06Q30/0645

Abstract: An object of the invention is to optimize a storage cost for data. There is provided a storage system including a storage device, a memory, and a processor configured to control input and output of data to and from the storage device. The processor monitors a storage amount that is at least one of a write amount (a total amount of data received as a write target) and a physical use amount (a total amount of data physically stored in the storage device), and a read amount (a total amount of data that is read), and calculates a fee as a storage cost that is a cost related to use of the storage device in a target period, based on a storage amount and a read amount in the target period in accordance with a monitoring result.

公开(公告)号：US11922018B2

公开(公告)日：2024-03-05

申请号：US17761782

申请日：2020-12-18

Applicant: HITACHI, LTD.

Inventor： Hiroaki Akutsu ,  Takahiro Naruko ,  Akifumi Suzuki

IPC: G06F3/06 ,  G06N3/08 ,  H03M7/30

CPC classification number: G06F3/0608 ,  G06F3/0659 ,  G06F3/0673 ,  G06N3/08 ,  H03M7/6041

Abstract: To generate an optimum compressor irrespective of the number of dimensions and a format of a multidimensional dataset. A storage system refers to dimension setting information, which is information representing an attribute for each of data dimensions of the multidimensional dataset, and generates a compressor based on the dimension setting information.

公开(公告)号：US20220269652A1

公开(公告)日：2022-08-25

申请号：US17673042

申请日：2022-02-16

Applicant: Hitachi, Ltd.

Inventor： Akifumi Suzuki ,  Hiroaki Akutsu

IPC: G06F16/174 ,  G06N3/08

Abstract: The computation load of computation using a neural network can be lowered. A computation apparatus has a prediction device, an encoder, and a decoder, and encodes and decodes data by using a probability density distribution. Of a learning process and a compression process, at least the compression process can be executed. By performing learning by using a neural network created by the learning process, a probability distribution table that causes a parameter and a symbol value probability distribution to correspond to each other can be used. In the compression process, the prediction device calculates the parameter from input data, and the encoder compresses the input data by using the symbol value probability distribution on the basis of the calculated parameter and the probability distribution table.

公开(公告)号：US10552044B2

公开(公告)日：2020-02-04

申请号：US15124690

申请日：2014-03-27

Applicant: Hitachi, Ltd.

Inventor： Yoshiki Kurokawa ,  Satoru Watanabe ,  Yoshitaka Tsujimoto ,  Mitsuhiro Okada ,  Akifumi Suzuki

IPC: G06F12/02 ,  G06F3/06 ,  G06F16/2455 ,  G06F16/951

Abstract: A management controller controls a data buffer and a flash controller, which controls I/O of data to and from flash memories, based on a search request. A data decompression engine includes a plurality of data decompression circuits for decompressing, in parallel, the compressed data transferred from the data buffer. A data search engine includes a plurality of data search circuits for searching, in parallel, data which satisfies search conditions among the respective data that were decompressed by the data decompression circuits, and transfers, to the search request source, the data obtained in the search performed by the data search circuits, wherein the flash controller reads, in parallel, a plurality of compressed data requested in the search request, and transfers the read compressed data to the data buffer, and the management controller transfers the compressed data to the data decompression engine when the compressed data is stored in the data buffer.

公开(公告)号：US10154113B2

公开(公告)日：2018-12-11

申请号：US15505751

申请日：2014-10-17

Applicant: HITACHI, LTD.

Inventor： Tetsuro Honmura ,  Yoshifumi Fujikawa ,  Keisuke Hatasaki ,  Mitsuhiro Okada ,  Akifumi Suzuki

IPC: G06F12/08 ,  H04L29/08 ,  G06F3/06 ,  G06F12/0804 ,  G06F12/0868 ,  G06F12/0875

Abstract: A computer system according to one preferred embodiment of the present invention has a server and a storage subsystem, wherein the server is configured to enable data write to a cache area of the storage subsystem. Further, the server manages the usages of the cache area. When storing data from the server to the cache area, the server determines whether a data-writable area exists in the cache area or not. If there is a writable area, data is stored in the writable area.

公开(公告)号：US10102070B2

公开(公告)日：2018-10-16

申请号：US15531795

申请日：2015-06-01

Applicant: Hitachi, Ltd.

Inventor： Shimpei Nomura ,  Akifumi Suzuki ,  Mitsuhiro Okada ,  Satoshi Morishita

IPC: G06F11/00 ,  G06F11/10 ,  G06F3/06 ,  G06F12/0804

Abstract: A purpose is to speed up a write process with a parity update. An information processing system includes storage devices constituting a RAID group, coupled to one bus and communicating with each other. Each of the storage devices includes a device controller and a storage medium for storing data. The storage devices include a first storage device storing old data and a second storage device storing old parity associated with the old data. A first device controller of the first storage device creates intermediate parity based on the old data and new data for updating the old data and transmit the intermediate parity to the second storage device specifying the second storage device storing the old parity associated with the old data, and a second device controller of the second storage device creates new parity based on the intermediate parity and the old parity.