公开(公告)号：US20200285520A1

公开(公告)日：2020-09-10

申请号：US16552146

申请日：2019-08-27

Applicant: HITACHI, LTD.

Inventor： Kazushi Nakagawa ,  Yoshifumi Fujikawa ,  Satoru Watanabe ,  Toshiyuki Aritsuka

IPC: G06F9/50 ,  G06F9/48 ,  G06F9/38 ,  G06F16/2453 ,  G06F16/28

Abstract: Processing performance is improved through introduction of accelerators and availability of the system is enhanced during introduction of the accelerators. A worker node includes a processor such as CPU, an accelerator that executes accelerator processing on a command, and a software model that operates on the CPU and executes software model processing of the command. In the worker node, the CPU breaks down an accelerator operator included in a query plan into a plurality of accelerator commands, sends each of the accelerator commands to the accelerator or the software model, and switches the destination of the accelerator command from the accelerator to the software model when a switching condition for changing the processing component of the accelerator command is satisfied.

公开(公告)号：US11151141B2

公开(公告)日：2021-10-19

申请号：US16549447

申请日：2019-08-23

Applicant: HITACHI, LTD.

Inventor： Yoshifumi Fujikawa ,  Toshiyuki Aritsuka ,  Satoru Watanabe ,  Kazushi Nakagawa ,  Kazuhisa Fujimoto ,  Masahiro Arai

IPC: G06F16/245 ,  G06F16/22 ,  G06F16/2453

Abstract: It is possible execute processing large-scale data and improve the processing efficiency while suppressing the complexity of a hardware circuit. A data processing device includes a processor and a FPGA connected to the processor. The processor is configured to acquire a query plan including target identification information identifying data to be processed and a processing detail for the data to be processed, generate, based on the query plan, a plurality of FPGA commands to process a plurality of row group data items constituting the data identified by the target identification information and to be processed, and transmit the FPGA commands to the FPGA. The FPGA is configured to execute processing on the row group data items based on the transmitted FPGA commands and return results of executing the processing to the processor.

公开(公告)号：US10154113B2

公开(公告)日：2018-12-11

申请号：US15505751

申请日：2014-10-17

Applicant: HITACHI, LTD.

Inventor： Tetsuro Honmura ,  Yoshifumi Fujikawa ,  Keisuke Hatasaki ,  Mitsuhiro Okada ,  Akifumi Suzuki

IPC: G06F12/08 ,  H04L29/08 ,  G06F3/06 ,  G06F12/0804 ,  G06F12/0868 ,  G06F12/0875

Abstract: A computer system according to one preferred embodiment of the present invention has a server and a storage subsystem, wherein the server is configured to enable data write to a cache area of the storage subsystem. Further, the server manages the usages of the cache area. When storing data from the server to the cache area, the server determines whether a data-writable area exists in the cache area or not. If there is a writable area, data is stored in the writable area.

公开(公告)号：US11366695B2

公开(公告)日：2022-06-21

申请号：US16125145

申请日：2018-09-07

Applicant: HITACHI, LTD.

Inventor： Yoshifumi Fujikawa ,  Kazuhisa Fujimoto ,  Toshiyuki Aritsuka ,  Kazushi Nakagawa

IPC: G06F9/50 ,  H04L41/5054 ,  H04L47/78

Abstract: A charging assistant system that assists charging for use of an accelerator unit, which is one or more accelerators, includes an operation amount obtaining unit, an acceleration rate estimation unit, and a use fee determination unit. For each of one or more commands input into the accelerator unit, the operation amount obtaining unit obtains the amount of operation related to execution of the command from a response output from the accelerator unit for the command. For the one or more commands input into the accelerator unit, the acceleration rate estimation unit estimates an acceleration rate on the basis of command execution time that is time required for processing of the one or more commands, and one or more amounts of operation obtained for the one or more commands respectively. The use fee determination unit determines a use fee of the accelerator unit on the basis of the estimated acceleration rate.

公开(公告)号：US20200265052A1

公开(公告)日：2020-08-20

申请号：US16549447

申请日：2019-08-23

Applicant: HITACHI, LTD.

Inventor： Yoshifumi Fujikawa ,  Toshiyuki Aritsuka ,  Satoru Watanabe ,  Kazushi Nakagawa ,  Kazuhisa Fujimoto ,  Masahiro Arai

IPC: G06F16/245 ,  G06F16/2453 ,  G06F16/22

Abstract: It is possible execute processing large-scale data and improve the processing efficiency while suppressing the complexity of a hardware circuit. A data processing device includes a processor and a FPGA connected to the processor. The processor is configured to acquire a query plan including target identification information identifying data to be processed and a processing detail for the data to be processed, generate, based on the query plan, a plurality of FPGA commands to process a plurality of row group data items constituting the data identified by the target identification information and to be processed, and transmit the FPGA commands to the FPGA. The FPGA is configured to execute processing on the row group data items based on the transmitted FPGA commands and return results of executing the processing to the processor.