知搜-全球专利检索

  1. 登录
  2. 注册

搜索结果

42 条记录 (耗时 0.027 秒)

    Systems and methods for selectively closing pages in a memory
    1.
    发明授权
    Systems and methods for selectively closing pages in a memory 失效
    选择性地关闭存储器中的页面的系统和方法

    公开(公告)号：US08140825B2

    公开(公告)日：2012-03-20

    申请号：US12185964

    申请日：2008-08-05

    申请人： Ganesh Balakrishnan ,  Anil Krishna ,  Michael R. Trombley

    发明人： Ganesh Balakrishnan ,  Anil Krishna ,  Michael R. Trombley

    IPC分类号： G06F12/00 ,  G06F9/26 ,  G06F9/34 ,  G06F15/00 ,  G06F7/38 ,  G06F9/00 ,  G06F9/44

    CPC分类号： G06F12/0215

    摘要： Systems, methods and media for selectively closing pages in a memory in anticipation of a context switch are disclosed. In one embodiment, a table is provided to keep track of open pages for different processes. The table comprises rows corresponding to banks of memory and columns corresponding to cores of a multi-core processing system. When a context switch signal is received, the system unsets a bit in a column corresponding to the core from which the process is to be context-switched out. If no other process is using a page opened by the process the page is closed.

    摘要翻译： 公开了用于在预期上下文切换中选择性地关闭存储器中的页面的系统，方法和介质。 在一个实施例中，提供了用于跟踪不同进程的打开页面的表格。 该表包括与多核处理系统的核心相对应的存储体组和列的行。 当接收到上下文切换信号时，系统取消对应于该进程将上下文切换出的核心的列中的位。 如果没有其他进程正在使用页面打开的页面关闭。

    Systems and Methods for Selectively Closing Pages in a Memory
    2.
    发明申请
    Systems and Methods for Selectively Closing Pages in a Memory 失效
    选择性地关闭内存页面的系统和方法

    公开(公告)号：US20100037034A1

    公开(公告)日：2010-02-11

    申请号：US12185964

    申请日：2008-08-05

    申请人： Ganesh Balakrishnan ,  Anil Krishna ,  Michael R. Trombley

    发明人： Ganesh Balakrishnan ,  Anil Krishna ,  Michael R. Trombley

    IPC分类号： G06F12/10

    CPC分类号： G06F12/0215

    摘要： Systems, methods and media for selectively closing pages in a memory in anticipation of a context switch are disclosed. In one embodiment, a table is provided to keep track of open pages for different processes. The table comprises rows corresponding to banks of memory and columns corresponding to cores of a multi-core processing system. When a context switch signal is received, the system unsets a bit in a column corresponding to the core from which the process is to be context-switched out. If no other process is using a page opened by the process the page is closed.

    摘要翻译： 公开了用于在预期上下文切换中选择性地关闭存储器中的页面的系统，方法和介质。 在一个实施例中，提供了用于跟踪不同进程的打开页面的表格。 该表包括与多核处理系统的核心相对应的存储体组和列的行。 当接收到上下文切换信号时，系统取消对应于该进程将上下文切换出的核心的列中的位。 如果没有其他进程正在使用页面打开的页面关闭。

    Memory system with apparatus and method to enable balanced bandwidth utilization
    7.
    发明授权
    Memory system with apparatus and method to enable balanced bandwidth utilization 失效
    具有使平衡带宽利用的装置和方法的存储器系统

    公开(公告)号：US07286543B2

    公开(公告)日：2007-10-23

    申请号：US10370550

    申请日：2003-02-20

    申请人： Brian M. Bass ,  Gordon T. Davis ,  Michael S. Siegel ,  Michael R. Trombley

    发明人： Brian M. Bass ,  Gordon T. Davis ,  Michael S. Siegel ,  Michael R. Trombley

    IPC分类号： H04L12/28 ,  H04J3/24

    CPC分类号： H04L49/9042 ,  H04L49/90 ,  H04L2012/5681

    摘要： A memory subsystem includes Data Store 0 and Data Store 1. Each data store is partitioned into N buffers, N>1. An increment of memory is formed by a buffer pair, with each buffer of the buffer pair being in a different data store. Two buffer pair formats are used in forming memory increments. A first format selects a first buffer from Data Store 0 and a second buffer from Data Store 1, while a second format selects a first buffer from Data Store 1 and a second buffer from Data Store 0. A controller selects a buffer pair for storing data based upon the configuration of data in a delivery mechanism, such as switch cell.

    摘要翻译： 存储器子系统包括数据存储0和数据存储1.每个数据存储分区为N个缓冲区，N> 1。 存储器的增量由缓冲器对形成，缓冲器对的每个缓冲器在不同的数据存储器中。 两个缓冲器对格式用于形成存储器增量。 第一格式从Data Store 0中选择第一个缓冲区，从Data Store 1中选择第二个缓冲区，而第二个格式从Data Store 1中选择第一个缓冲区，并从Data Store 0中选择一个第二个缓冲区。控制器选择一个用于存储数据的缓冲区 基于诸如交换单元之类的递送机制中的数据的配置。

    Memory access alignment in a double data rate (‘DDR’) system
    8.
    发明授权
    Memory access alignment in a double data rate (‘DDR’) system 有权
    双数据速率（“DDR”）系统中的存储器访问对齐

    公开(公告)号：US08547760B2

    公开(公告)日：2013-10-01

    申请号：US13171811

    申请日：2011-06-29

    申请人： Steven K. Jenkins ,  Robert B. Likovich, Jr. ,  Michael R. Trombley

    发明人： Steven K. Jenkins ,  Robert B. Likovich, Jr. ,  Michael R. Trombley

    IPC分类号： G11C8/18

    CPC分类号： G06F3/0605 ,  G06F3/0659 ,  G06F3/0673 ,  G06F12/00 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/1093 ,  G11C11/40 ,  G11C11/40622 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/2254 ,  G11C2207/2272

    摘要： Memory access alignment in a double data rate (‘DDR’) system, including: executing, by a memory controller, one or more write operations to a predetermined address of a DDR memory module, including sending to the DDR memory module a predetermined amount of data of a predetermined pattern along with a data strobe signal; executing, by the memory controller, a plurality of read operations from the predetermined address of the DDR memory module, including capturing data transmitted from the DDR memory module; and determining, by the memory controller, a read adjust value and a write adjust value in dependence upon the data captured in response to the read operations.

    摘要翻译： 在双数据速率（“DDR”）系统中的存储器访问对准，包括：由存储器控制器执行对DDR存储器模块的预定地址的一个或多个写入操作，包括向DDR存储器模块发送预定量的 预定图案的数据以及数据选通信号; 由所述存储器控制器执行来自所述DDR存储器模块的预定地址的多个读取操作，包括捕获从所述DDR存储器模块发送的数据; 以及由存储器控制器根据读取操作所捕获的数据确定读取调整值和写入调整值。

    Error correcting code protected quasi-static bit communication on a high-speed bus
    9.
    发明授权
    Error correcting code protected quasi-static bit communication on a high-speed bus 失效
    在高速总线上纠错代码保护的准静态位通信

    公开(公告)号：US08234540B2

    公开(公告)日：2012-07-31

    申请号：US12165788

    申请日：2008-07-01

    申请人： Peter Buchmann ,  Kevin C. Gower ,  Robert J. Reese ,  Martin L. Schmatz ,  Michael R. Trombley

    发明人： Peter Buchmann ,  Kevin C. Gower ,  Robert J. Reese ,  Martin L. Schmatz ,  Michael R. Trombley

    IPC分类号： H03M13/00

    CPC分类号： H03M13/13 ,  G06F11/10

    摘要： A communication interface device, system, method, and design structure for error correcting code (ECC) protected quasi-static bit communication (SBC) on a high-speed bus are provided. The communication interface device includes high-speed sampling logic to capture high-speed data from the high-speed bus using a high-speed sampling clock and SBC sampling logic to capture SBC samples from the high-speed bus using an SBC sampling clock. The SBC sampling clock is slower than the high-speed sampling clock. The communication interface device also includes an SBC finite state machine (FSM) to detect a received SBC command in response to a static pattern persisting for a predetermined number of the SBC samples and command decoding logic to decode the received SBC command.

    摘要翻译： 提供了一种用于在高速总线上进行纠错码（ECC）保护的准静态位通信（SBC）的通信接口设备，系统，方法和设计结构。 通信接口设备包括高速采样逻辑，以使用高速采样时钟和SBC采样逻辑从高速总线捕获高速数据，以使用SBC采样时钟从高速总线捕获SBC采样。 SBC采样时钟比高速采样时钟慢。 通信接口设备还包括SBC有限状态机（FSM），以响应于持续预定数量的SBC采样的静态模式和用于解码所接收的SBC命令的命令解码逻辑来检测接收到的SBC命令。

    Structure for reducing latency associated with read operations in a memory system
    10.
    发明授权
    Structure for reducing latency associated with read operations in a memory system 失效
    用于减少与存储器系统中的读取操作相关联的延迟的结构

    公开(公告)号：US08140803B2

    公开(公告)日：2012-03-20

    申请号：US12114787

    申请日：2008-05-04

    申请人： James J. Allen, Jr. ,  Steven K. Jenkins ,  James A. Mossman ,  Michael R. Trombley

    发明人： James J. Allen, Jr. ,  Steven K. Jenkins ,  James A. Mossman ,  Michael R. Trombley

    IPC分类号： G06F12/00 ,  G06F13/00

    CPC分类号： G06F13/1689

    摘要： A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design is provided. The design structure generally includes a processor memory system, which may include a processor and a memory controller in communication with the processor through a bus. The memory controller may include a delay circuit to receive an early read indicator corresponding to read data from a memory, the delay circuit to delay the early read indicator in accordance with a pre-determined delay such that the early read indicator is passed to the bus in advance of the read data, and a delay adjustment circuit to dynamically adjust the pre-determined delay associated with the delay circuit responsive to a change in operational speed of the processor or the bus.

    摘要翻译： 提供了体现在用于设计，制造和/或测试设计的机器可读存储介质中的设计结构。 设计结构通常包括处理器存储器系统，其可以包括处理器和通过总线与处理器通信的存储器控​​制器。 存储器控制器可以包括延迟电路，用于接收对应于来自存储器的读取数据的早期读取指示符，延迟电路根据预定的延迟来延迟早期读取指示符，使得早期读取指示符被传递到总线 以及延迟调整电路，用于响应于处理器或总线的操作速度的变化来动态地调整与延迟电路相关联的预定延迟。