公开(公告)号：US09099380B2

公开(公告)日：2015-08-04

申请号：US14511811

申请日：2014-10-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Vara Govindeswara Reddy Vakada ,  Laegu Kang ,  Michael P. Ganz ,  Yi Qi ,  Puneet Khanna ,  Sri Charan Vemula ,  Srikanth Samavedam

IPC: H01L29/167 ,  H01L29/04 ,  H01L29/16 ,  H01L29/66 ,  H01L27/088

CPC classification number: H01L29/167 ,  H01L21/2205 ,  H01L21/26506 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/088 ,  H01L27/092 ,  H01L29/04 ,  H01L29/105 ,  H01L29/1054 ,  H01L29/1079 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66477 ,  H01L29/66651

Abstract: A methodology enabling the formation of steep channel profiles for devices, such as SSRW FETs, having a resultant channel profiles that enables suppression of threshold voltage variation and the resulting device are disclosed. Embodiments include providing STI regions in a silicon wafer; performing a deep well implantation of a dopant into the silicon wafer between STI regions; forming a recess in the doped silicon wafer between the STI regions; performing a shallow well implantation of the dopant into the silicon wafer in the recess; and forming Si:C on the doped silicon wafer in the recess.

Abstract translation: 公开了一种使得能够形成具有能够抑制阈值电压变化的结果信道分布和所得到的器件的诸如SSRW FET的器件的陡峭通道轮廓的方法。 实施例包括在硅晶片中提供STI区域; 在STI区域之间对硅晶片进行深阱注入掺杂剂; 在所述STI区域之间的所述掺杂硅晶片中形成凹部; 在所述凹部中进行所述掺杂剂的浅阱注入到所述硅晶片中; 并在凹陷中的掺杂硅晶片上形成Si：C。

公开(公告)号：US20150270346A1

公开(公告)日：2015-09-24

申请号：US14731644

申请日：2015-06-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Kuldeep Amarnath ,  Michael Hargrove ,  Srikanth Samavedam

IPC: H01L29/10 ,  H01L29/08 ,  H01L29/423

CPC classification number: H01L29/1033 ,  H01L29/0847 ,  H01L29/42376 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66621 ,  H01L29/66636 ,  H01L29/7848

Abstract: Disclosed herein are various methods of forming replacement gate structures with a recessed channel region. In one example, the method includes forming a sacrificial gate structure above a semiconducting substrate, removing the sacrificial gate structure to thereby define an initial gate opening having sidewalls and to expose a surface of the substrate and performing an etching process on the exposed surface of the substrate to define a recessed channel in the substrate. The method includes the additional steps of forming a sidewall spacer within the initial gate opening on the sidewalls of the initial gate opening to thereby define a final gate opening and forming a replacement gate structure in the final gate opening.

Abstract translation: 本文公开了形成具有凹陷沟道区域的替换栅极结构的各种方法。 在一个示例中，该方法包括在半导体衬底之上形成牺牲栅极结构，去除牺牲栅极结构，从而限定具有侧壁的初始栅极开口并暴露衬底的表面，并在衬底的暴露表面上执行蚀刻工艺 衬底以在衬底中限定凹陷通道。 该方法包括在初始栅极开口的侧壁上的初始栅极开口内形成侧壁间隔物以由此限定最终栅极开口并在最终栅极开口中形成替换栅极结构的附加步骤。

公开(公告)号：US09362357B2

公开(公告)日：2016-06-07

申请号：US14716045

申请日：2015-05-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Laegu Kang ,  Vara Govindeswara Reddy Vakada ,  Michael Ganz ,  Yi Qi ,  Puneet Khanna ,  Sri Charan Vemula ,  Srikanth Samavedam

IPC: H01L29/06 ,  H01L21/762 ,  H01L29/66 ,  H01L29/10 ,  H01L21/8238 ,  H01L29/167 ,  H01L29/165

CPC classification number: H01L29/0692 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/823892 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/1095 ,  H01L29/165 ,  H01L29/167 ,  H01L29/66651

Abstract: A method of forming SSRW FETs with controlled step height between a field oxide and epitaxially grown silicon and the resulting devices are provided. Embodiments include providing a SiN layer on a substrate, forming first, second, and third spaced STI regions of field oxide through the SiN layer and into the substrate, removing a top portion of the field oxide for each STI region by a controlled deglaze, removing the SiN layer, forming an n-type region in the substrate between the first and second STI regions and a p-type region in the substrate between the second and third STI regions, and epitaxially growing a Si based layer on the substrate over the n-type and p-type regions.

公开(公告)号：US08916442B2

公开(公告)日：2014-12-23

申请号：US13743886

申请日：2013-01-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Vara Govindeswara Reddy Vakada ,  Laegu Kang ,  Michael P. Ganz ,  Yi Qi ,  Puneet Khanna ,  Sri Charan Vemula ,  Srikanth Samavedam

IPC: H01L29/66 ,  H01L27/088

CPC classification number: H01L29/167 ,  H01L21/2205 ,  H01L21/26506 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/088 ,  H01L27/092 ,  H01L29/04 ,  H01L29/105 ,  H01L29/1054 ,  H01L29/1079 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66477 ,  H01L29/66651

Abstract: A methodology enabling the formation of steep channel profiles for devices, such as SSRW FETs, having a resultant channel profiles that enables suppression of threshold voltage variation and the resulting device are disclosed. Embodiments include providing STI regions in a silicon wafer; performing a deep well implantation of a dopant into the silicon wafer between STI regions; forming a recess in the doped silicon wafer between the STI regions; performing a shallow well implantation of the dopant into the silicon wafer in the recess; and forming Si:C on the doped silicon wafer in the recess.

Abstract translation: 公开了一种使得能够形成具有能够抑制阈值电压变化的结果信道分布和所得到的器件的诸如SSRW FET的器件的陡峭通道轮廓的方法。 实施例包括在硅晶片中提供STI区域; 在STI区域之间对硅晶片进行深阱注入掺杂剂; 在所述STI区域之间的所述掺杂硅晶片中形成凹部; 在所述凹部中进行所述掺杂剂的浅阱注入到所述硅晶片中; 并在凹陷中的掺杂硅晶片上形成Si：C。