公开(公告)号：US10522655B2

公开(公告)日：2019-12-31

申请号：US15711674

申请日：2017-09-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： George Robert Mulfinger ,  Ryan Sporer ,  Rick J. Carter ,  Peter Baars ,  Hans-Jürgen Thees ,  Jan Höntschel

IPC: H01L29/66 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12 ,  H01L29/78 ,  H01L29/08

Abstract: A method of forming matched PFET/NFET spacers with differential widths for SG and EG structures and a method of forming differential width nitride spacers for SG NFET and SG PFET structures and PFET/NFET EG structures and respective resulting devices are provided. Embodiments include providing PFET SG and EG structures and NFET SG and EG structures; forming a first nitride layer over the substrate; forming an oxide liner; forming a second nitride layer on sidewalls of the PFET and NFET EG structures; removing horizontal portions of the first nitride layer and the oxide liner over the PFET SG and EG structures; forming RSD structures on opposite sides of each of the PFET SG and EG structures; removing horizontal portions of the first nitride layer and the oxide liner over the NFET SG and EG structures; and forming RSD structures on opposite sides of each of the NFET SG and EG structures.

公开(公告)号：US10326007B2

公开(公告)日：2019-06-18

申请号：US16026820

申请日：2018-07-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： George Robert Mulfinger ,  Ryan Sporer ,  Timothy J. McArdle ,  Judson Robert Holt

IPC: H01L29/94 ,  H01L29/66 ,  H01L21/84 ,  H01L21/225 ,  H01L21/02 ,  H01L29/08 ,  H01L29/78 ,  H01L29/10 ,  H01L27/12 ,  H01L21/8238 ,  H01L27/092

Abstract: Methods of forming a graded SiGe percentage PFET channel in a FinFET or FDSOI device by post gate thermal condensation and oxidation of a high Ge percentage channel layer and the resulting devices are provided. Embodiments include forming a gate dielectric layer over a plurality of Si fins; forming a gate over each fin; forming a HM and spacer layer over and on sidewalls of each gate; forming a cavity in each fin adjacent to the gate and spacer layer; epitaxially growing an un-doped high percentage SiGe layer in each cavity and along sidewalls of each fin; thermally condensing the high percentage SiGe layer, an un-doped low percentage SiGe formed underneath in the substrate and fins; and forming a S/D region over the high percentage SiGe layer in each u-shaped cavity, an upper surface of the S/D regions below the gate dielectric layer.

公开(公告)号：US10217660B2

公开(公告)日：2019-02-26

申请号：US15652585

申请日：2017-07-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ryan Sporer ,  George Mulfinger

IPC: H01L21/762 ,  H01L21/8234 ,  H01L21/84 ,  H01L21/308 ,  H01L29/06

Abstract: When patterning active regions for sophisticated semiconductor devices, the cutting through active semiconductor regions previously patterned along a first lateral direction so as to obtain elongated semiconductor lines may be performed in a late manufacturing stage. That is, the cutting may be performed after patterning at least a portion of the gate electrode structures, thereby achieving a self-aligned patterning regime and also contributing to a reduction of strain loss.

公开(公告)号：US10050119B2

公开(公告)日：2018-08-14

申请号：US15256027

申请日：2016-09-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： George Robert Mulfinger ,  Dina H. Triyoso ,  Ryan Sporer

IPC: H01L27/12 ,  H01L29/66 ,  H01L29/78 ,  H01L29/772 ,  H01L27/088 ,  H01L21/324 ,  H01L29/06 ,  H01L29/417 ,  H01L29/51 ,  H01L21/84 ,  H01L29/786

Abstract: Methods for selectively thinning a silicon channel area under a gate electrode and resulting devices are disclosed. Embodiments include providing a SOI substrate including a Si-layer; providing a first dummy-gate electrode over a first gate-oxide between first spacers over a first channel area of the Si-layer and a second dummy-gate electrode over a second gate-oxide between second spacers over a second channel area of the Si-layer; forming a S/D region adjacent each spacer; forming an oxide over the S/D regions and the spacers; removing the dummy-gate electrodes creating first and second cavities between respective first and second spacers; forming a mask with an opening over the first cavity; removing the first gate-oxide; thinning the Si-layer under the first cavity, forming a recess in the Si-layer; forming a third gate-oxide on recess side and bottom surfaces; and filling the recess and the cavities with metal, forming first and second RMG electrodes.

公开(公告)号：US20190027400A1

公开(公告)日：2019-01-24

申请号：US15652585

申请日：2017-07-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ryan Sporer ,  George Mulfinger

IPC: H01L21/762 ,  H01L21/8234 ,  H01L21/84 ,  H01L21/308 ,  H01L29/06

Abstract: When patterning active regions for sophisticated semiconductor devices, the cutting through active semiconductor regions previously patterned along a first lateral direction so as to obtain elongated semiconductor lines may be performed in a late manufacturing stage. That is, the cutting may be performed after patterning at least a portion of the gate electrode structures, thereby achieving a self-aligned patterning regime and also contributing to a reduction of strain loss.

公开(公告)号：US10056381B2

公开(公告)日：2018-08-21

申请号：US15259268

申请日：2016-09-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ryan Sporer ,  Amy Child ,  George Mulfinger

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/10 ,  H01L21/225 ,  H01L21/308 ,  H01L21/324 ,  H01L29/167

CPC classification number: H01L27/0924 ,  H01L21/2256 ,  H01L21/308 ,  H01L21/324 ,  H01L21/823821 ,  H01L29/1083 ,  H01L29/167

Abstract: Device structures for a FinFET and fabrication methods for making a device structure for a FinFET. A first layer containing a first dopant is formed on a first region of a substrate. A second layer containing a second dopant is formed on a second region of the substrate. A first plurality of fins are formed and are each located in a respective trench extending from the substrate through the first layer. A second plurality of fins are formed and are each located in a respective trench extending from the substrate through the second layer. The first dopant is transferred from the first layer to a first section in each of the first plurality of fins and the second dopant is transferred from the second layer to a first section in each of the second plurality of fins.

公开(公告)号：US10043893B1

公开(公告)日：2018-08-07

申请号：US15668012

申请日：2017-08-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： George Robert Mulfinger ,  Ryan Sporer ,  Timothy J. McArdle ,  Judson Robert Holt

IPC: H01L29/94 ,  H01L29/66 ,  H01L21/84 ,  H01L21/225 ,  H01L21/02 ,  H01L29/08 ,  H01L29/78 ,  H01L29/10 ,  H01L27/12

Abstract: Methods of forming a graded SiGe percentage PFET channel in a FinFET or FDSOI device by post gate thermal condensation and oxidation of a high Ge percentage channel layer and the resulting devices are provided. Embodiments include forming a gate dielectric layer over a plurality of Si fins formed over a substrate; forming a gate over each fin; forming a HM and spacer layer over and on sidewalls of each gate; forming a u-shaped cavity in each fin adjacent to the gate and spacer layer; epitaxially growing an un-doped high percentage SiGe layer in each u-shaped cavity and along sidewalls of each fin; thermally condensing the high percentage SiGe layer, an un-doped low percentage SiGe formed underneath in the substrate and fins; and forming a S/D region over the high percentage SiGe layer in each u-shaped cavity, an upper surface of the S/D regions below the gate dielectric layer.

公开(公告)号：US20180069005A1

公开(公告)日：2018-03-08

申请号：US15259268

申请日：2016-09-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ryan Sporer ,  Amy Child ,  George Mulfinger

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/10 ,  H01L21/225 ,  H01L21/308 ,  H01L21/324 ,  H01L29/167

CPC classification number: H01L27/0924 ,  H01L21/2256 ,  H01L21/308 ,  H01L21/324 ,  H01L21/823821 ,  H01L29/1083 ,  H01L29/167

Abstract: Device structures for a FinFET and fabrication methods for making a device structure for a FinFET. A first layer containing a first dopant is formed on a first region of a substrate. A second layer containing a second dopant is formed on a second region of the substrate. A first plurality of fins are formed and are each located in a respective trench extending from the substrate through the first layer. A second plurality of fins are formed and are each located in a respective trench extending from the substrate through the second layer. The first dopant is transferred from the first layer to a first section in each of the first plurality of fins and the second dopant is transferred from the second layer to a first section in each of the second plurality of fins.

公开(公告)号：US09875936B1

公开(公告)日：2018-01-23

申请号：US15348109

申请日：2016-11-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ryan Sporer ,  Rohit Pal ,  Jeremy Wahl

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/304 ,  H01L21/306 ,  H01L21/308 ,  H01L29/04 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/762 ,  H01L21/3105 ,  H01L27/088 ,  H01L27/092

CPC classification number: H01L21/823431 ,  H01L21/31053 ,  H01L21/76224 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/6653 ,  H01L29/66795

Abstract: Methods for forming fins with a straight profile by preventing fin bending during STI fill and annealing are disclosed. Embodiments include providing STI regions separated by Si regions, each topped with a hardmask; planarizing the STI regions; removing the hardmask over a portion of the Si regions, forming recesses; forming a conformal spacer layer over the STI regions and in the recesses; removing horizontal portions of the spacer layer; epitaxially growing Si in each recess, forming fins; and etching the STI regions and a remainder of the spacer layer down to the Si regions to reveal the fins.

公开(公告)号：US09806170B1

公开(公告)日：2017-10-31

申请号：US15151550

申请日：2016-05-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： George Robert Mulfinger ,  Ryan Sporer ,  Rick J. Carter ,  Peter Baars ,  Hans-Jürgen Thees ,  Jan Höntschel

IPC: H01L21/20 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/66 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/78

CPC classification number: H01L29/6656 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L21/84 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/161 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66628 ,  H01L29/7838

Abstract: A method of forming matched PFET/NFET spacers with differential widths for SG and EG structures and a method of forming differential width nitride spacers for SG NFET and SG PFET structures and PFET/NFET EG structures and respective resulting devices are provided. Embodiments include providing PFET SG and EG structures and NFET SG and EG structures; forming a first nitride layer over the substrate; forming an oxide liner; forming a second nitride layer on sidewalls of the PFET and NFET EG structures; removing horizontal portions of the first nitride layer and the oxide liner over the PFET SG and EG structures; forming RSD structures on opposite sides of each of the PFET SG and EG structures; removing horizontal portions of the first nitride layer and the oxide liner over the NFET SG and EG structures; and forming RSD structures on opposite sides of each of the NFET SG and EG structures.