公开(公告)号：US20220130953A1

公开(公告)日：2022-04-28

申请号：US17572274

申请日：2022-01-10

Applicant: General Electric Company

Inventor： Stephen Daley Arthur ,  Victor Mario Torres ,  Michael J. Hartig ,  Reza Ghandi ,  David Alan Lilienfeld ,  Alexander Viktorovich Bolotnikov

IPC: H01L29/06 ,  H01L29/16 ,  H01L21/04 ,  H01L29/66

Abstract: A disclosed super-junction (SJ) device includes a first epitaxial (epi) layer that forms a first SJ layer of the SJ device, and includes a second epi layer disposed on the first SJ layer that forms a device layer of the SJ device. An active area of the first and second epi layers includes a first set of SJ pillars comprising a particular doping concentration of a first conductivity type and a second set of SJ pillars comprising the particular doping concentration of a second conductivity type. A termination area of the first and second epi layers has a minimized epi doping concentration of the first conductivity type that is less than the particular doping concentration, and the termination area of the second epi layer includes a plurality of floating regions of the second conductivity type that form a junction termination of the SJ device.

公开(公告)号：US11271076B2

公开(公告)日：2022-03-08

申请号：US16517222

申请日：2019-07-19

Applicant: General Electric Company

Inventor： Stephen Daley Arthur ,  Victor Mario Torres ,  Michael J. Hartig ,  Reza Ghandi ,  David Alan Lilienfeld ,  Alexander Viktorovich Bolotnikov

IPC: H01L29/15 ,  H01L31/0312 ,  H01L29/06 ,  H01L29/16 ,  H01L21/04 ,  H01L29/66

Abstract: The subject matter disclosed herein relates to semiconductor power devices and, more specifically, to junction termination designs for wide-bandgap (e.g., silicon carbide) semiconductor power devices. A disclosed semiconductor device includes a first epitaxial (epi) layer disposed on a substrate layer, wherein a termination area of the first epi layer has a minimized epi doping concentration of a first conductivity type (e.g., n-type). The device also includes a second epi layer disposed on the first epi layer, wherein a termination area of the second epi layer has the minimized epi doping concentration of the first conductivity type and includes a first plurality of floating regions of a second conductivity type (e.g., p-type) that form a first junction termination of the device.

公开(公告)号：US10957759B2

公开(公告)日：2021-03-23

申请号：US16235486

申请日：2018-12-28

Applicant: General Electric Company

Inventor： Stephen Daley Arthur ,  Reza Ghandi ,  Alexander Viktorovich Bolotnikov ,  David Alan Lilienfeld ,  Peter Almern Losee

IPC: H01L29/06 ,  H01L29/16 ,  H01L21/04 ,  H01L29/66

Abstract: A silicon carbide (SiC) charge balance (CB) device includes a CB layer, which includes a first epitaxial (epi) layer. An active area of the first epi layer includes a first doping concentration of a first conductivity type and a first plurality of CB regions of a second conductivity type. A termination area of the first epi layer includes a minimized epi doping concentration of the first conductivity type. The SiC—CB device also includes a device layer, which includes a second epi layer disposed on the CB layer. An active area of the second epi layer includes the first doping concentration of the first conductivity type. A termination area of the device layer includes the minimized epi doping concentration of the first conductivity type and a first plurality of floating regions of the second conductivity type that form a junction termination of the device.

公开(公告)号：US20190245035A1

公开(公告)日：2019-08-08

申请号：US15890077

申请日：2018-02-06

Applicant: General Electric Company

Inventor： Reza Ghandi ,  David Alan Lilienfeld ,  Alexander Viktorovich Bolotnikov ,  Peter Almern Losee

IPC: H01L29/06 ,  H01L29/16 ,  H01L21/02 ,  H01L21/761 ,  H01L21/265 ,  H01L21/324 ,  H01L27/088 ,  H01L27/092

CPC classification number: H01L29/0646 ,  H01L21/02529 ,  H01L21/26506 ,  H01L21/324 ,  H01L21/761 ,  H01L27/088 ,  H01L27/092 ,  H01L29/1608

Abstract: An integrated circuit includes a silicon carbide (SiC) epitaxial layer disposed on a SiC layer, wherein the SiC epitaxial layer has a first conductivity-type and the SiC layer has a second conductivity-type that is opposite to the first conductivity-type. The integrated circuit also includes a junction isolation feature disposed in the SiC epitaxial layer and having the second conductivity-type. The junction isolation feature extends vertically through a thickness of the SiC epitaxial layer and contacts the SiC layer, and wherein the junction isolation feature has a depth of at least about 2 micrometers (μm).

公开(公告)号：US20190140048A1

公开(公告)日：2019-05-09

申请号：US16010531

申请日：2018-06-18

Applicant: General Electric Company

Inventor： Alexander Viktorovich Bolotnikov ,  Reza Ghandi ,  David Alan Lilienfeld ,  Peter Almern Losee

IPC: H01L29/06 ,  H01L21/04 ,  H01L29/20 ,  H01L21/266 ,  H01L29/78 ,  H01L21/265 ,  H01L29/16

Abstract: The subject matter disclosed herein relates to super-junction (SJ) power devices and, more specifically, to edge termination techniques for SJ power devices. A semiconductor super-junction (SJ) device includes one or more epitaxial (epi) layers having a termination region disposed adjacent to an active region. The termination region includes a plurality of vertical pillars of a first and a second conductivity-type, wherein, moving outward from the active region, a respective width of each successive vertical pillar is the same or smaller. The termination region also includes a plurality of compensated regions having a low doping concentration disposed directly between a first side of each vertical pillar of the first conductivity-type and a first side of each vertical pillar of the second conductivity-type, wherein, moving outward from the active region, a respective width of each successive compensated region is the same or greater.

公开(公告)号：US10243039B2

公开(公告)日：2019-03-26

申请号：US15077579

申请日：2016-03-22

Applicant: General Electric Company

Inventor： Alexander Viktorovich Bolotnikov ,  Peter Almern Losee ,  David Alan Lilienfeld ,  Reza Ghandi

IPC: H01L21/04 ,  H01L29/06 ,  H01L29/16 ,  H01L29/66 ,  H01L29/73 ,  H01L29/78 ,  H01L29/732 ,  H01L29/808 ,  H01L29/861 ,  H01L29/872

Abstract: A super junction (SJ) device may include one or more charge balance (CB) layers. Each CB layer may include an epitaxial (epi) layer having a first conductivity type and a plurality of charge balance (CB) regions having a second conductivity type. Additionally, the SJ device may include a connection region having the second conductivity type that extends from a region disposed in a top surface of a device layer of the SJ device to one or more of the CB regions. The connection region may enable carriers to flow directly from the region to the one or more CB regions, which may decrease switching losses of the SJ device.

公开(公告)号：US20180166531A1

公开(公告)日：2018-06-14

申请号：US15379214

申请日：2016-12-14

Applicant: General Electric Company

Inventor： Alexander Viktorovich Bolotnikov ,  Reza Ghandi ,  David Alan Lilienfeld ,  Peter Almern Losee

IPC: H01L29/06 ,  H01L29/36 ,  H01L29/16 ,  H01L29/20 ,  H01L21/265 ,  H01L21/266

CPC classification number: H01L29/0634 ,  H01L21/26506 ,  H01L21/266 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/36

Abstract: The subject matter disclosed herein relates to super-junction (SJ) power devices and, more specifically, to edge termination techniques for SJ power devices. A semiconductor super-junction (SJ) device includes one or more epitaxial (epi) layers having a termination region disposed adjacent to an active region. The termination region includes a plurality of vertical pillars of a first and a second conductivity-type, wherein, moving outward from the active region, a respective width of each successive vertical pillar is the same or smaller. The termination region also includes a plurality of compensated regions having a low doping concentration disposed directly between a first side of each vertical pillar of the first conductivity-type and a first side of each vertical pillar of the second conductivity-type, wherein, moving outward from the active region, a respective width of each successive compensated region is the same or greater.

公开(公告)号：US20170345890A1

公开(公告)日：2017-11-30

申请号：US15164928

申请日：2016-05-26

Applicant: GENERAL ELECTRIC COMPANY

Inventor： Peter Almern Losee ,  Alexander Viktorovich Bolotnikov ,  Yang Sui

IPC: H01L29/06 ,  H01L29/16 ,  H01L21/761 ,  H01L29/10 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/0623 ,  H01L21/761 ,  H01L29/0619 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/66333 ,  H01L29/66712 ,  H01L29/7395 ,  H01L29/7811 ,  H01L29/7832 ,  H01L29/872

Abstract: Embodiments of a semiconductor device and methods of forming thereof are provided herein. In some embodiments, a power semiconductor device may include a first layer having a first conductivity type; a second layer disposed atop the first layer, the second layer having the first conductivity type; a termination region formed in the second layer, the termination region having a second conductivity type opposite the first type; and an active region at least partially formed in the second layer, wherein the active region is disposed adjacent to the termination region proximate a first side of the termination region and wherein the second layer is at least partially disposed adjacent to the termination region proximate a second side of the termination region opposite the first side.

公开(公告)号：US20160099318A1

公开(公告)日：2016-04-07

申请号：US14505975

申请日：2014-10-03

Applicant: General Electric Company

Inventor： Alexander Viktorovich Bolotnikov ,  Avinash Srikrishnan Kashyap

IPC: H01L29/16 ,  H01L27/02 ,  H01L27/08 ,  H01L29/861 ,  H01L29/66

CPC classification number: H01L29/1608 ,  H01L27/0255 ,  H01L27/0814 ,  H01L29/6606 ,  H01L29/861

Abstract: A transient voltage suppression (TVS) device and a method of forming the device are provided. The TVS device includes a first layer of wide band-gap semiconductor material formed of a first conductivity type material, a second layer of wide band-gap semiconductor material formed of a second conductivity type material over at least a portion of the first layer, the second layer including a first concentration of dopant. The TVS device further including a third layer of wide band-gap semiconductor material formed of the second conductivity type material over at least a portion of the second layer, the third layer including a second concentration of dopant, the second concentration of dopant being different than the first concentration of dopant. The TVS device further including a fourth layer of wide band-gap semiconductor material formed of the first conductivity type material over at least a portion of the third layer.

Abstract translation: 提供瞬态电压抑制（TVS）装置和形成装置的方法。 TVS器件包括由第一导电类型材料形成的第一层宽带隙半导体材料，在第一层的至少一部分上由第二导电类型材料形成的第二层宽带隙半导体材料， 第二层包括掺杂剂的第一浓度。 TVS器件还包括在第二层的至少一部分上由第二导电类型材料形成的第三层宽带隙半导体材料，第三层包括第二浓度的掺杂剂，第二掺杂剂浓度不同于 掺杂剂的第一个浓度。 TVS器件还包括在第三层的至少一部分上由第一导电类型材料形成的第四层宽带隙半导体材料。

公开(公告)号：US09123798B2

公开(公告)日：2015-09-01

申请号：US13712188

申请日：2012-12-12

Applicant: General Electric Company

Inventor： Stephen Daley Arthur ,  Kevin Sean Matocha ,  Ramakrishna Rao ,  Peter Losee ,  Alexander Viktorovich Bolotnikov

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/16

CPC classification number: H01L29/7802 ,  H01L27/088 ,  H01L29/1083 ,  H01L29/1608 ,  H01L29/42368 ,  H01L29/66068 ,  H01L29/66712 ,  H03K17/687

Abstract: An insulating gate field effect transistor (IGFET) device includes a semiconductor body and a gate oxide. The semiconductor body includes a first well region doped with a first type of dopant and a second well region that is doped with an oppositely charged second type of dopant and is located within the first well region. The gate oxide includes an outer section and an interior section having different thickness dimensions. The outer section is disposed over the first well region and the second well region of the semiconductor body. The interior section is disposed over a junction gate field effect transistor region of the semiconductor body. The semiconductor body is configured to form a conductive channel through the second well region and the junction gate field effect transistor region when a gate signal is applied to a gate contact disposed on the gate oxide.

Abstract translation: 绝缘栅场效应晶体管（IGFET）器件包括半导体本体和栅极氧化物。 半导体本体包括掺杂有第一类型掺杂剂的第一阱区域和掺杂有相反电荷的第二类型掺杂剂并位于第一阱区域内的第二阱区域。 栅极氧化物包括具有不同厚度尺寸的外部部分和内部部分。 外部部分设置在半导体本体的第一阱区域和第二阱区域的上方。 内部部分设置在半导体本体的结栅场效应晶体管区域的上方。 半导体本体被配置为当栅极信号施加到设置在栅极氧化物上的栅极触点时，通过第二阱区域和结栅场效应晶体管区域形成导电沟道。