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公开(公告)号：US12062552B2
公开(公告)日：2024-08-13
申请号：US17516545
申请日：2021-11-01
发明人： Yuma Murata , Ryoichi Kato , Takashi Saito , Ryotaro Tsuruoka
摘要： A method for manufacturing a semiconductor device includes obtaining a shear stress FT at which that a value obtained by dividing a loss elastic modulus by a storage elastic modulus equals 1 for each of a plurality of candidate heat conductive greases at each of a plurality of temperatures that are within a prescribed control temperature range determined based on an operation temperature range of the semiconductor device to be manufactured; selecting a heat conductive grease, among the plurality of candidate heat conductive greases, that has a value of FT of 100 Pa or more and 200 Pa or less at each of the plurality of the temperatures within the prescribed control temperature range; and attaching a resin sealed body that includes a semiconductor element mounted on a laminated substrate therein to a cooler via the heat conductive grease that has been selected in the selecting.
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2.发明授权公开(公告)号：US12029017B2
公开(公告)日：2024-07-02
申请号：US17365053
申请日：2021-07-01
发明人： Ryoichi Kato
摘要： A semiconductor module has a heat conduction section provided between a multilayer substrate, on which semiconductor chips are mounted, and a cooler. The heat conduction section includes a frame and an opening, and the opening has a grease portion which is provided partly in the opening and is in contact with the multilayer substrate and the cooler, and a space portion which is provided between the grease portion and the frame in a partial and band-shaped manner.
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公开(公告)号：US10128345B2
公开(公告)日：2018-11-13
申请号：US15792772
申请日：2017-10-25
发明人： Ryoichi Kato , Hiromichi Gohara , Takafumi Yamada , Kohei Yamauchi , Tatsuhiko Asai , Yoshitaka Nishimura , Akio Kitamura , Hajime Masubuchi , Souichi Yoshida
IPC分类号： H01L29/423 , H01L23/492 , H01L23/367 , H01L23/28 , H01L29/739 , H01L23/00
摘要： A semiconductor device including a semiconductor element, an upper-surface electrode provided on an upper surface of the semiconductor element, a plated layer provided on an upper surface of the upper-surface electrode, one or more gate runners penetrating the plated layer and provided to extend in a predetermined direction on the upper surface of the semiconductor element, and a metal connecting plate that is arranged above the plated layer and is electrically connected to the upper-surface electrode, wherein the metal connecting plate has a joint portion parallel to the upper surface of the semiconductor element and has a rising portion that is connected to a first end of the joint portion and extends in a direction away from the upper surface of the semiconductor element, and in a plane parallel to the upper surface of the semiconductor element, the rising portion and the gate runner do not overlap with each other.
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公开(公告)号：US12072155B2
公开(公告)日：2024-08-27
申请号：US17472509
申请日：2021-09-10
发明人： Akihito Aoki , Eiji Anzai , Yoshinari Ikeda , Hiromichi Gohara , Ryoichi Kato , Michihiro Inaba , Tetsuya Sunago
IPC分类号： F28F9/02 , F28F1/02 , H01L23/367
CPC分类号： F28F9/0246 , F28F1/02 , H01L23/367
摘要： A cooling device includes a body having a flow passage for a heating medium that passes through the body, a first header made of a resin that has an inlet and covers a first end, and a second header made of a resin that has an outlet and covers a second end. The body has a front face, a back face, a first side face, and a second side face. The body and the first header are bonded to a first bonding face, a second bonding face, a third bonding face, and a fourth bonding face. The third bonding face is a curved surface that protrudes toward a +Y side. The fourth bonding face is a curved surface that protrudes toward a −Y side.
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公开(公告)号：US11705419B2
公开(公告)日：2023-07-18
申请号：US17139065
申请日：2020-12-31
IPC分类号： H01L21/768 , H01L23/522 , H01L27/088 , H10B41/27 , H10B43/27 , H01L23/00 , H01L23/538 , H01L29/739 , H01L21/50 , H01L21/60
CPC分类号： H01L24/14 , H01L21/50 , H01L23/5385 , H01L23/5386 , H01L24/95 , H01L29/7393 , H01L2021/60022
摘要： A semiconductor module includes a laminated substrate having an insulating plate, a circuit pattern arranged on an upper surface of the insulating plate and a heat dissipating plate arranged on a lower surface of the insulating plate. The semiconductor module also includes a semiconductor device having a collector electrode arranged on its upper surface, having an emitter electrode and a gate electrode arranged on its lower surface, and bumps respectively bonding the emitter electrode and the gate electrode to an upper surface of the circuit pattern. Each of the bumps is made of a metal sintered material such that the bump is formed to be constricted in its middle portion in a thickness direction orthogonal to a surface of the insulating plate.
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公开(公告)号：US11309276B2
公开(公告)日：2022-04-19
申请号：US17185931
申请日：2021-02-25
发明人： Yuma Murata , Ryoichi Kato , Naoyuki Kanai , Akito Nakagome , Yoshinari Ikeda
IPC分类号： H01L23/00 , H01L23/538 , H01L25/07
摘要： A semiconductor module includes a case with a side wall in a first direction in which gate and source terminals are embodied and exposed therefrom, first and second semiconductor elements each having gate and source electrodes, gate and source relay layers positioned at a center between the first and second semiconductor elements in the first direction at a side of the semiconductor elements farther from the side wall, first gate and source wires respectively connecting the gate and source terminals to the gate and source relay layers, second gate and source wires, and third gate and source wires, respectively connecting the gate and source electrodes of the first semiconductor element, and the gate and source electrode of the second semiconductor element, to the gate and source relay layers. The first to third source wires are respectively located closer to the first to third gate wires than any other gate wires.
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公开(公告)号：US10916491B2
公开(公告)日：2021-02-09
申请号：US16120754
申请日：2018-09-04
发明人： Ryoichi Kato , Kohei Yamauchi , Hiromichi Gohara , Tatsuhiko Asai
IPC分类号： H01L23/495 , H01L23/492 , H01L23/367 , H01L23/00 , H01L29/739 , H01L23/36 , H01L23/498 , H01L23/04 , H01L23/373 , H01L23/24
摘要： A semiconductor module includes a semiconductor element having one and the other surface, a lead terminal connected electrically and thermally to the semiconductor element, a first solder which bonds the lead terminal and the one surface of the semiconductor element together, a circuit layer over which the semiconductor element is disposed and a second solder which bonds the other surface of the semiconductor element and the circuit layer together. The inequality (A/B)
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公开(公告)号：US10276474B2
公开(公告)日：2019-04-30
申请号：US15091957
申请日：2016-04-06
IPC分类号： H01L23/367 , H01L21/48 , H01L23/498 , H01L23/373 , H01L23/40 , H01L23/00 , H01L25/07
摘要： A semiconductor device includes a plurality of semiconductor elements; insulating circuit boards each including an insulating substrate, a circuit portion on a front surface of the insulating substrate connected to one semiconductor element, and a metal portion on a rear surface of the insulating substrate; a metal plate joined to the metal portions of the plurality of insulating circuit boards; and a joint member joining the plurality of insulating circuit boards to the metal plate. The metal plate has a front surface in which the insulating circuit boards are arranged apart from each other, and a rear surface including first regions corresponding to positions of the metal portions and second regions other than the first regions. At least a part of a surface of each of the first regions has a surface work-hardened layer, and the second regions have a hardness different from that of the surface work-hardened layer.
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公开(公告)号：US09871006B2
公开(公告)日：2018-01-16
申请号：US15243971
申请日：2016-08-23
发明人： Ryoichi Kato , Takafumi Yamada , Hiromichi Gohara
IPC分类号： H01L23/367 , H01L23/00 , H01L23/473 , H01L21/48 , H01L23/373
CPC分类号： H01L23/562 , H01L21/4882 , H01L23/3672 , H01L23/3735 , H01L23/473 , H01L24/29 , H01L24/32 , H01L2224/291 , H01L2224/32227 , H01L2924/3511 , H01L2924/014
摘要： A semiconductor module including an insulated circuit substrate having a substrate, a circuit layer on a front surface of the substrate, and a metal layer on a back surface of the substrate; a semiconductor element electrically connected to the circuit layer; a cooling unit having a ceiling board bonded to the metal layer, a bottom board opposite the ceiling board, a side wall connecting a periphery of the ceiling board and a periphery of the bottom board, and a fin connecting the ceiling board and bottom board, where thickness of the ceiling board is at least 0.5 mm and at most 2.0 mm and total thickness of the ceiling board and bottom board is at least 3 mm and at most 6 mm; and a solder layer that bonds together the metal layer and the ceiling board by melting at a temperature of at least 200° C. and at most 350° C.
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公开(公告)号：US11887925B2
公开(公告)日：2024-01-30
申请号：US17883074
申请日：2022-08-08
发明人： Ryoichi Kato , Yoshinari Ikeda , Yuma Murata
IPC分类号： H01L23/522 , H01L23/49 , H01L23/498 , H01L25/16 , H01R4/02 , H01R43/02
CPC分类号： H01L23/5222 , H01L23/49 , H01L23/49811 , H01L25/162 , H01R4/029 , H01R43/0221
摘要： A capacitor includes a case including a capacitor element, a first connection terminal, a second connection terminal, and a second insulating sheet formed between the first connection terminal and the second connection terminal, and the first connection terminal, the second insulating sheet, and the second connection terminal extend to the outside from the case. A semiconductor module includes a multi-layer terminal portion in which a first power terminal, a first insulating sheet, and a second power terminal are sequentially stacked. The first power terminal includes a first bonding area electrically connected to the first connection terminal, and the second power terminal includes a second bonding area electrically connected to the second connection terminal. The first insulating sheet includes a terrace portion that extends in a direction from the second bonding area towards the first bonding area in a planar view.
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