知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

9 records (took 0.017 seconds)

    SRAM device including oxide semiconductor
    1.
    发明授权
    SRAM device including oxide semiconductor 有权

    公开(公告)号：US11895817B2

    公开(公告)日：2024-02-06

    申请号：US17529817

    申请日：2021-11-18

    Applicant: Electronics and Telecommunications Research Institute

    Inventor： Sung Haeng Cho ,  Byung-Do Yang ,  Sooji Nam ,  Jaehyun Moon ,  Jae-Eun Pi ,  Jae-Min Kim

    IPC: H10B10/00 ,  G11C11/417 ,  G11C11/412

    CPC classification number: H10B10/12 ,  G11C11/412 ,  G11C11/417

    Abstract: Provided is a static random-access memory (SRAM) device. The SRAM device includes a substrate including a PMOS area, a circuit wiring structure including an insulating layer and a wiring layer alternately stacked on the substrate, wherein the circuit wiring structure includes a first NMOS area and a second NMOS area vertically separated from the PMOS area with the first NMOS area therebetween, a first transistor including a first gate electrode disposed on the PMOS area, source/drain areas formed on the PMOS area on both sides of the first gate electrode, and a first channel connecting the source and drain areas to each other, a second transistor including a second gate electrode disposed in the first NMOS area and a second channel vertically overlapping the second gate electrode, and a third transistor including a third gate electrode disposed in the second NMOS area and a third channel vertically overlapping the third gate electrode, wherein the first channel includes silicon, wherein the second channel and the third channel include an oxide semiconductor.

    CMOS logic element including oxide semiconductor
    4.
    发明授权
    CMOS logic element including oxide semiconductor 有权

    公开(公告)号：US12237331B2

    公开(公告)日：2025-02-25

    申请号：US17520853

    申请日：2021-11-08

    Applicant: Electronics and Telecommunications Research Institute

    Inventor： Sung Haeng Cho ,  Byung-Do Yang ,  Sooji Nam ,  Jaehyun Moon ,  Jae-Eun Pi ,  Jae-Min Kim

    IPC: H01L27/02 ,  H01L27/092 ,  H01L29/24 ,  H03K19/018 ,  H03K19/0185 ,  H03K19/0948

    Abstract: Provided is a Complementary Metal Oxide Semiconductor (CMOS) logic element. The CMOS logic element includes a substrate including a PMOS area, a circuit wiring structure including an insulating layer and a wiring layer alternately stacked on the substrate, wherein the circuit wiring structure includes an NMOS area vertically spaced apart from the PMOS area, a first transistor disposed on the PMOS area, and a second transistor disposed on the NMOS area and complementarily connected to the first transistor, wherein the first transistor includes a first gate electrode, source/drain areas formed on the PMOS area on both sides of the first gate electrode, and a first channel connecting the source and drain areas to each other, wherein the second transistor includes a second gate electrode and a second channel vertically overlapping the second gate electrode, wherein the first channel includes silicon, wherein the second channel includes an oxide semiconductor.

    Stretchable display
    8.
    发明授权
    Stretchable display 有权

    公开(公告)号：US10741777B2

    公开(公告)日：2020-08-11

    申请号：US16204869

    申请日：2018-11-29

    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

    Inventor： Chi-Sun Hwang ,  Seung Youl Kang ,  Byoung-Hwa Kwon ,  Gi Heon Kim ,  Seong Hyun Kim ,  Jaehyun Moon ,  Young Sam Park ,  Seongdeok Ahn ,  Jeong Ik Lee ,  Sung Haeng Cho

    IPC: H01L51/00 ,  H01L51/52 ,  H01L51/56 ,  H01L27/32 ,  B32B7/12 ,  B32B27/08

    Abstract: Provided is a stretchable display including an elastic body, a light emitting unit on the elastic body, and a wiring unit on the elastic body, wherein the light emitting unit includes a first substrate unit on the elastic body, a buffer layer on the first substrate unit, and a light emitting element on the buffer layer, the wiring unit includes a second substrate unit on the elastic body, a driving element configured to control the light emitting element, a wiring configured to electrically connect the driving element and the light emitting element, and an insulation layer configured to cover the driving element and the wiring, the light emitting unit and the wiring unit have respective corrugation structures, a thickness of the light emitting unit is larger than that of the wiring unit, a modulus of elasticity of the buffer layer is larger than that of the insulation layer, and a modulus of elasticity of the elastic body is smaller than that of the insulation layer.

    Transistor and method of fabricating the same
    9.
    发明授权
    Transistor and method of fabricating the same 有权
    晶体管及其制造方法

    公开(公告)号：US09105726B2

    公开(公告)日：2015-08-11

    申请号：US14192239

    申请日：2014-02-27

    Applicant: Electronics and Telecommunications Research Institute

    Inventor： Sung Haeng Cho ,  Sang-Hee Park ,  Chi-Sun Hwang

    IPC: H01L29/786 ,  H01L29/66 ,  H01L29/417

    CPC classification number: H01L29/41775 ,  H01L29/0847 ,  H01L29/41733 ,  H01L29/41758 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/786 ,  H01L29/78603 ,  H01L29/7869

    Abstract: Provided is a transistor. The transistor includes: a substrate; a semiconductor layer provided on the substrate and having one side vertical to the substrate and the other side facing the one side; a first electrode extending along the substrate and contacting the one side of the semiconductor layer; a second electrode extending along the substrate and contacting the other side of the semiconductor layer; a conductive wire disposed on the first electrode and spaced from the second electrode; a gate electrode provided on the semiconductor layer; and a gate insulating layer disposed between the semiconductor layer and the gate electrode, wherein the semiconductor layer, the first electrode, and the second electrode have a coplanar.

    Abstract translation: 提供一种晶体管。 晶体管包括：衬底; 半导体层，其设置在所述基板上，并且具有与所述基板垂直的一侧，所述另一侧面向所述一侧; 沿所述基板延伸并接触所述半导体层的一侧的第一电极; 第二电极，沿着衬底延伸并接触半导体层的另一侧; 布置在所述第一电极上并与所述第二电极间隔开的导线; 设置在所述半导体层上的栅电极; 以及设置在所述半导体层和所述栅电极之间的栅绝缘层，其中所述半导体层，所述第一电极和所述第二电极具有共面。

Patent Agency Ranking