公开(公告)号：US12237331B2

公开(公告)日：2025-02-25

申请号：US17520853

申请日：2021-11-08

Applicant: Electronics and Telecommunications Research Institute

Inventor： Sung Haeng Cho ,  Byung-Do Yang ,  Sooji Nam ,  Jaehyun Moon ,  Jae-Eun Pi ,  Jae-Min Kim

IPC: H01L27/02 ,  H01L27/092 ,  H01L29/24 ,  H03K19/018 ,  H03K19/0185 ,  H03K19/0948

Abstract: Provided is a Complementary Metal Oxide Semiconductor (CMOS) logic element. The CMOS logic element includes a substrate including a PMOS area, a circuit wiring structure including an insulating layer and a wiring layer alternately stacked on the substrate, wherein the circuit wiring structure includes an NMOS area vertically spaced apart from the PMOS area, a first transistor disposed on the PMOS area, and a second transistor disposed on the NMOS area and complementarily connected to the first transistor, wherein the first transistor includes a first gate electrode, source/drain areas formed on the PMOS area on both sides of the first gate electrode, and a first channel connecting the source and drain areas to each other, wherein the second transistor includes a second gate electrode and a second channel vertically overlapping the second gate electrode, wherein the first channel includes silicon, wherein the second channel includes an oxide semiconductor.

公开(公告)号：US11895817B2

公开(公告)日：2024-02-06

申请号：US17529817

申请日：2021-11-18

Applicant: Electronics and Telecommunications Research Institute

Inventor： Sung Haeng Cho ,  Byung-Do Yang ,  Sooji Nam ,  Jaehyun Moon ,  Jae-Eun Pi ,  Jae-Min Kim

IPC: H10B10/00 ,  G11C11/417 ,  G11C11/412

CPC classification number: H10B10/12 ,  G11C11/412 ,  G11C11/417

Abstract: Provided is a static random-access memory (SRAM) device. The SRAM device includes a substrate including a PMOS area, a circuit wiring structure including an insulating layer and a wiring layer alternately stacked on the substrate, wherein the circuit wiring structure includes a first NMOS area and a second NMOS area vertically separated from the PMOS area with the first NMOS area therebetween, a first transistor including a first gate electrode disposed on the PMOS area, source/drain areas formed on the PMOS area on both sides of the first gate electrode, and a first channel connecting the source and drain areas to each other, a second transistor including a second gate electrode disposed in the first NMOS area and a second channel vertically overlapping the second gate electrode, and a third transistor including a third gate electrode disposed in the second NMOS area and a third channel vertically overlapping the third gate electrode, wherein the first channel includes silicon, wherein the second channel and the third channel include an oxide semiconductor.