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    System and method for integrated circuits with cylindrical gate structures
    1.
    发明申请
    System and method for integrated circuits with cylindrical gate structures 有权
    具有圆柱形栅极结构的集成电路的系统和方法

    公开(公告)号：US20110291190A1

    公开(公告)日：2011-12-01

    申请号：US12892881

    申请日：2010-09-28

    申请人： De Yuan Xiao ,  Guo Qing Chen ,  Roger Lee ,  Chin Fu Yen ,  Su Xing ,  Xiao Lu Huang ,  Yong Sheng Yang

    发明人： De Yuan Xiao ,  Guo Qing Chen ,  Roger Lee ,  Chin Fu Yen ,  Su Xing ,  Xiao Lu Huang ,  Yong Sheng Yang

    IPC分类号： H01L29/772 ,  H01L21/28 ,  H01L21/336

    CPC分类号： H01L29/0673 ,  B82Y10/00 ,  H01L21/28035 ,  H01L21/31133 ,  H01L21/324 ,  H01L21/84 ,  H01L29/0665 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/42392 ,  H01L29/4916 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7854 ,  H01L29/78696

    摘要： A system and method for integrated circuits with surrounding gate structures are disclosed. The integrated circuits system includes a transistor having a gate all around cylindrical (GAAC) nanowire channel with an interposed dielectric layer. The cylindrical nanowire channel being in a middle section of a semiconductor wire pattern connects the source and drain region positioned at the two opposite end sections of the same wire pattern. A method is provided for manufacturing the integrate circuits system with a GAAC transistor including forming an SOI layer wire pattern on the buried oxide layer of an SOI wafer; forming a cavity underneath the middle section of the wire pattern and shaping the middle section to cylindrically shaped channel; forming a gate electrode surrounding the cylindrical channel region with an interposed gate dielectric layer, the gate electrode being positioned on the buried oxide layer vertically towards the wire pattern; forming the source/drain regions at the two opposite end sections of the wire pattern on either sides of the gate electrode and channel.

    摘要翻译： 公开了一种具有周围栅极结构的集成电路的系统和方法。 集成电路系统包括晶体管，其具有围绕圆柱形（GAAC）纳米线通道的栅极，具有插入的介电层。 位于半导体布线图案的中间部分的圆柱形纳米线通道连接位于相同导线图案的两个相对端部处的源极和漏极区域。 提供了一种用于制造具有包括在SOI晶片的掩埋氧化物层上形成SOI层布线图案的GAAC晶体管的集成电路系统的方法; 在导线图案的中间部分下方形成空腔，并将中间部分成形为圆柱形通道; 用插入的栅极介电层形成围绕所述圆柱形沟道区的栅电极，所述栅电极垂直于所述导线图案位于所述掩埋氧化物层上; 在栅极电极和沟道的任一侧上的导线图案的两个相对端部处形成源极/漏极区域。

    System and method for integrated circuits with cylindrical gate structures
    4.
    发明授权
    System and method for integrated circuits with cylindrical gate structures 有权
    具有圆柱形栅极结构的集成电路的系统和方法

    公开(公告)号：US08884363B2

    公开(公告)日：2014-11-11

    申请号：US12892881

    申请日：2010-09-28

    申请人： De Yuan Xiao ,  Guo Qing Chen ,  Roger Lee ,  Chin Fu Yen ,  Su Xing ,  Xiao Lu Huang ,  Yong Sheng Yang

    发明人： De Yuan Xiao ,  Guo Qing Chen ,  Roger Lee ,  Chin Fu Yen ,  Su Xing ,  Xiao Lu Huang ,  Yong Sheng Yang

    IPC分类号： H01L29/66 ,  H01L29/423 ,  H01L29/06 ,  B82Y10/00 ,  H01L29/78 ,  H01L29/786

    CPC分类号： H01L29/0673 ,  B82Y10/00 ,  H01L21/28035 ,  H01L21/31133 ,  H01L21/324 ,  H01L21/84 ,  H01L29/0665 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/42392 ,  H01L29/4916 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7854 ,  H01L29/78696

    摘要： A system and method for integrated circuits with surrounding gate structures are disclosed. The integrated circuits system includes a transistor having a gate all around cylindrical (GAAC) nanowire channel with an interposed dielectric layer. The cylindrical nanowire channel being in a middle section of a semiconductor wire pattern connects the source and drain region positioned at the two opposite end sections of the same wire pattern. A method is provided for manufacturing the integrate circuits system with a GAAC transistor including forming an SOI layer wire pattern on the buried oxide layer of an SOI wafer; forming a cavity underneath the middle section of the wire pattern and shaping the middle section to cylindrically shaped channel; forming a gate electrode surrounding the cylindrical channel region with an interposed gate dielectric layer, the gate electrode being positioned on the buried oxide layer vertically towards the wire pattern; forming the source/drain regions at the two opposite end sections of the wire pattern on either sides of the gate electrode and channel.

    摘要翻译： 公开了一种具有周围栅极结构的集成电路的系统和方法。 集成电路系统包括晶体管，其具有围绕圆柱形（GAAC）纳米线通道的栅极，具有插入的介电层。 位于半导体布线图案的中间部分的圆柱形纳米线通道连接位于相同导线图案的两个相对端部处的源极和漏极区域。 提供了一种用于制造具有包括在SOI晶片的掩埋氧化物层上形成SOI层布线图案的GAAC晶体管的集成电路系统的方法; 在导线图案的中间部分下方形成空腔，并将中间部分成形为圆柱形通道; 用插入的栅极介电层形成围绕所述圆柱形沟道区的栅电极，所述栅电极垂直于所述导线图案位于所述掩埋氧化物层上; 在栅极电极和沟道的任一侧上的导线图案的两个相对端部处形成源极/漏极区域。

    3-D electrically programmable and erasable single-transistor non-volatile semiconductor memory device
    7.
    发明授权
    3-D electrically programmable and erasable single-transistor non-volatile semiconductor memory device 有权
    3-D电可编程和可擦除单晶体管非易失性半导体存储器件

    公开(公告)号：US08471323B2

    公开(公告)日：2013-06-25

    申请号：US12880039

    申请日：2010-09-10

    申请人： De Yuan Xiao ,  Gary Chen ,  Roger Lee

    发明人： De Yuan Xiao ,  Gary Chen ,  Roger Lee

    IPC分类号： H01L29/788

    CPC分类号： H01L29/7885 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/66825

    摘要： A non-volatile memory device includes a source region, a drain region, and a channel region therebetween. The channel region has a length extending from the source region to the drain region and a channel width in the direction perpendicular to the channel length direction. The device includes a floating gate positioned between the source and the drain in the channel length direction. The width of the floating gate is less than the channel width. A control gate covers a top surface and a side surface of the floating gate. The control gate also overlies an entirety of the channel region. Erasure of the cell is accomplished by Fowler-Nordheim tunneling from the floating gate to the control gate. Programming is accomplished by electrons migrating through an electron concentration gradient from a channel region underneath the control gate into a channel region underneath the floating gate and then injecting into the floating gate.

    摘要翻译： 非易失性存储器件包括源极区，漏极区和它们之间的沟道区。 沟道区域具有从源极区域到漏极区域的长度以及与沟道长度方向垂直的方向的沟道宽度。 该器件包括在沟道长度方向上位于源极和漏极之间的浮动栅极。 浮动栅极的宽度小于通道宽度。 控制栅极覆盖浮动栅极的顶表面和侧表面。 控制门也覆盖整个通道区域。 通过从浮动门到控制门的Fowler-Nordheim隧道实现对电池的擦除。 编程是通过电子从电子浓度梯度从控制栅极下方的沟道区域迁移到浮动栅极下方的沟道区域中，然后注入到浮动栅极中来实现的。