公开(公告)号：US20140362457A1

公开(公告)日：2014-12-11

申请号：US14331315

申请日：2014-07-15

Applicant: Cisco Technology, Inc.

Inventor： Mary NADEAU ,  Vipulkumar PATEL ,  Prakash GOTHOSKAR ,  John FANGMAN ,  John Matthew FANGMAN ,  Mark WEBSTER

IPC: G02B7/02 ,  G02B7/00 ,  H01L23/544

CPC classification number: G02B7/025 ,  G02B6/4228 ,  G02B6/4239 ,  G02B7/003 ,  H01L23/345 ,  H01L23/544 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L2223/54426 ,  H01L2224/26175 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/83121 ,  H01L2224/83143 ,  H01L2224/83192 ,  H01L2224/83234 ,  H01L2224/83385 ,  H01L2224/83862 ,  H01L2924/14 ,  Y10T428/24479 ,  H01L2924/0665 ,  H01L2924/00014 ,  H01L2924/00

Abstract: An arrangement for improving adhesive attachment of micro-components in an assembly utilizes a plurality of parallel-disposed slots formed in the top surface of the substrate used to support the micro-components. The slots are used to control the flow and “shape” of an adhesive “dot” so as to quickly and accurately attach a micro-component to the surface of a substrate. The slots are formed (preferably, etched) in the surface of the substrate in a manner that lends itself to reproducible accuracy from one substrate to another. Other slots (“channels”) may be formed in conjunction with the bonding slots so that extraneous adhesive material will flow into these channels and not spread into unwanted areas.

Abstract translation: 用于改善组件中微组件的粘合附着的装置利用形成在用于支撑微组件的衬底顶表面中的多个平行布置的槽。 这些槽用于控制粘合剂“点”的流动和“形状”，以便将微组件快速且精确地附着在基板的表面上。 在衬底的表面中形成（优选地，蚀刻）狭槽，使其自身具有从一个衬底到另一个衬底的可再现精度。 其它槽（“通道”）可以与结合槽结合形成，使得外来粘合剂材料将流入这些通道并且不会扩散到不需要的区域。

公开(公告)号：US20180188450A1

公开(公告)日：2018-07-05

申请号：US15899255

申请日：2018-02-19

Applicant: Cisco Technology, Inc.

Inventor： Vipulkumar PATEL ,  Mark WEBSTER ,  Ravi TUMMIDI ,  Mary NADEAU

IPC: G02B6/12 ,  G02B6/42 ,  G02B6/30 ,  G02B6/122

Abstract: Embodiments herein describe a photonic chip which includes a coupling interface for evanescently coupling the chip to a waveguide on an external substrate. In one embodiment, the photonic chip includes a tapered waveguide that aligns with a tapered waveguide on the external substrate. The respective tapers of the two waveguides are inverted such that as the width of the waveguide in the photonic chip decreases, the width of the waveguide on the external substrate increases. In one embodiment, these two waveguides form an adiabatic structure where the optical signal transfers between the waveguides with minimal or no coupling of the optical signal to other non-intended modes. Using the two waveguides, optical signals can be transmitted between the photonic chip and the external substrate.

公开(公告)号：US20220368102A1

公开(公告)日：2022-11-17

申请号：US17302964

申请日：2021-05-17

Applicant: Cisco Technology, Inc.

Inventor： Norbert SCHLEPPLE ,  Jock T. BOVINGTON ,  Mary NADEAU ,  Mittu PANNALA ,  Jarrett S. NEIMAN

IPC: H01S5/024 ,  H01S5/02 ,  H01S5/02326

Abstract: Heatsinking in laser devices may be improved via a device, including: a header disk having a first face with a circumference; a header post that is thermally conductive, and having: a second face connected to the first face coterminously with the circumference; a third face opposite to the second face; and a fourth face perpendicular to the second face and the third face; a lens holder, having a fifth face connected to the third face; and an optical subassembly connected to the fourth face and optically aligned with the lens holder. The device may also be understood to comprise: a header disk having a circumference; a header post that is thermally conductive, the header post having: an arc coterminous to a portion of the circumference; a mounting face, perpendicular to a plane in which the arc and the circumference are defined; and a bonding face perpendicular to the mounting face.

公开(公告)号：US20170003463A1

公开(公告)日：2017-01-05

申请号：US14790925

申请日：2015-07-02

Applicant: Cisco Technology, Inc.

Inventor： Mary NADEAU ,  Thomas DAUGHERTY ,  Ravi Sekhar TUMMIDI ,  Vipulkumar PATEL

IPC: G02B6/42 ,  H01S5/022 ,  H01S5/02 ,  G02B6/13

CPC classification number: H01S5/02272 ,  G02B6/4231 ,  G02B6/4238 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01S5/0224 ,  H01S5/02252 ,  H01L2924/00014

Abstract: Embodiments disclosed herein generally relate to a method for manufacturing a photonic device that facilitates precise alignment of a laser with a waveguide. The method generally includes disposing the laser on a support member on a substrate such that the laser contacts the support member. The support member may extend in a direction perpendicular to a base plane of the substrate, and solder may be disposed on the base plane such that a height of the solder in the direction perpendicular to the base plane is less than a height of the support member so that a gap is created between the solder and the laser. Once the laser has been properly aligned with the waveguide, the solder may be heated (e.g., reflowed) so that the solder contacts the laser.

Abstract translation: 本文公开的实施例一般涉及一种用于制造有助于激光与波导的精确对准的光子器件的方法。 该方法通常包括将激光器设置在基板上的支撑构件上，使得激光器接触支撑构件。 支撑构件可以在垂直于基底的基面的方向上延伸，并且焊料可以设置在基面上，使得焊料在垂直于基面的方向上的高度小于支撑构件的高度 从而在焊料和激光之间产生间隙。 一旦激光器已经正确地对准波导，则焊料可以被加热（例如回流），使得焊料接触激光器。

公开(公告)号：US20180233880A1

公开(公告)日：2018-08-16

申请号：US15431840

申请日：2017-02-14

Applicant: Cisco Technology, Inc.

Inventor： Mary NADEAU ,  Jarrett S. NEIMAN ,  Mittu PANNALA

IPC: H01S5/022 ,  H01S5/042 ,  H01S5/22

CPC classification number: H01S5/02236 ,  H01S5/0224 ,  H01S5/02248 ,  H01S5/02252 ,  H01S5/02256 ,  H01S5/02268 ,  H01S5/02276 ,  H01S5/0425 ,  H01S5/22

Abstract: A laser light source, a submount for a semiconductor laser, and a method of providing a laser light source are provided. The laser light source includes a submount with first and second electrical contacts thereon and a trench there-between. A semiconductor laser is bonded to the submount by bonding third and fourth electrical contacts of the laser to the first and second electrical contacts, respectively. The third and fourth electrical contacts of the laser are arranged on opposite side of a laser active stripe, which is arranged over the trench of the submount.

公开(公告)号：US20170139142A1

公开(公告)日：2017-05-18

申请号：US15143944

申请日：2016-05-02

Applicant: Cisco Technology, Inc.

Inventor： Vipulkumar PATEL ,  Mark WEBSTER ,  Ravi TUMMIDI ,  Mary NADEAU

IPC: G02B6/293 ,  G02B6/42 ,  G02B6/30

CPC classification number: G02B6/12004 ,  G02B6/12002 ,  G02B6/1228 ,  G02B6/124 ,  G02B6/125 ,  G02B6/305 ,  G02B6/34 ,  G02B6/4206 ,  G02B6/4274 ,  G02B6/4291

Abstract: Embodiments herein describe a photonic chip which includes a coupling interface for evanescently coupling the chip to a waveguide on an external substrate. In one embodiment, the photonic chip includes a tapered waveguide that aligns with a tapered waveguide on the external substrate. The respective tapers of the two waveguides are inverted such that as the width of the waveguide in the photonic chip decreases, the width of the waveguide on the external substrate increases. In one embodiment, these two waveguides form an adiabatic structure where the optical signal transfers between the waveguides with minimal or no coupling of the optical signal to other non-intended modes. Using the two waveguides, optical signals can be transmitted between the photonic chip and the external substrate.

公开(公告)号：US20170139132A1

公开(公告)日：2017-05-18

申请号：US15208658

申请日：2016-07-13

Applicant: Cisco Technology ,Inc.

Inventor： Vipulkumar PATEL ,  Mark WEBSTER ,  Ravi TUMMIDI ,  Mary NADEAU

IPC: G02B6/12 ,  G02B6/34 ,  G02B6/122 ,  G02B6/124 ,  G02B6/42 ,  G02B6/125

CPC classification number: G02B6/12004 ,  G02B6/12002 ,  G02B6/1228 ,  G02B6/124 ,  G02B6/125 ,  G02B6/305 ,  G02B6/34 ,  G02B6/4206 ,  G02B6/4274 ,  G02B6/4291

Abstract: The embodiments herein describe a photonic chip (formed from a SOI structure) which includes an optical interface for coupling the optical components in the photonic chip to an external optical device. In one embodiment, the optical interface is formed on a separate substrate which is later joined to the photonic chip. Through oxide vias (TOVs) and through silicon vias (TSVs) can be used to electrically couple the optical components in the photonic chip to external integrated circuits or amplifiers. In one embodiment, after the separate wafer is bonded to the photonic chip, a TOV is formed in the photonic chip to electrically connect metal routing layers coupled to the optical components in the photonic chip to a TSV in the separate wafer. For example, the TOV may extend across a wafer bonding interface where the two substrates where bonded to form an electrical connection with the TSV.