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    ELECTRO-OPTICAL MODULATOR USING WAVEGUIDES WITH OVERLAPPING RIDGES
    2.
    发明申请
    ELECTRO-OPTICAL MODULATOR USING WAVEGUIDES WITH OVERLAPPING RIDGES 有权

    公开(公告)号：US20220082875A1

    公开(公告)日：2022-03-17

    申请号：US17456468

    申请日：2021-11-24

    Applicant: Cisco Technology, Inc.

    Inventor： Donald ADAMS ,  Prakash B. GOTHOSKAR ,  Vipulkumar PATEL ,  Mark WEBSTER

    IPC: G02F1/025 ,  G02F1/01 ,  G02B6/132 ,  G02B6/136 ,  G02F1/225

    Abstract: An optical modulator may include a lower waveguide, an upper waveguide, and a dielectric layer disposed therebetween. When a voltage potential is created between the lower and upper waveguides, these layers form a silicon-insulator-silicon capacitor (also referred to as SISCAP) guide that provides efficient, high-speed optical modulation of an optical signal passing through the modulator. In one embodiment, at least one of the waveguides includes a respective ridge portion aligned at a charge modulation region which may aid in confining the optical mode laterally (e.g., in the width direction) in the optical modulator. In another embodiment, ridge portions may be formed on both the lower and the upper waveguides. These ridge portions may be aligned in a vertical direction (e.g., a thickness direction) so that ridges overlap which may further improve optical efficiency by centering an optical mode in the charge modulation region.

    WAFER SCALE PACKAGING PLATFORM FOR TRANSCEIVERS
    3.
    发明申请
    WAFER SCALE PACKAGING PLATFORM FOR TRANSCEIVERS 有权
    收货机的平均包装平台

    公开(公告)号：US20140248723A1

    公开(公告)日：2014-09-04

    申请号：US14276566

    申请日：2014-05-13

    Applicant: Cisco Technology, Inc.

    Inventor： Kalpendu SHASTRI ,  Vipulkumar PATEL ,  Mark WEBSTER ,  Prakash GOTHOSKAR ,  Ravinder KACHRU ,  Soham PATHAK ,  Rao V. YELAMARTY ,  Thomas DAUGHERTY ,  Bipin DAMA ,  Kaushik PATEL ,  Kishor DESAI

    IPC: H01L25/00 ,  H01L25/16

    CPC classification number: H01L25/50 ,  G02B6/423 ,  G02B6/4244 ,  G02B6/4245 ,  G02B6/4249 ,  G02B6/4257 ,  G02B6/426 ,  H01L25/167 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/00014

    Abstract: A wafer scale implementation of an opto-electronic transceiver assembly process utilizes a silicon wafer as an optical reference plane and platform upon which all necessary optical and electronic components are simultaneously assembled for a plurality of separate transceiver modules. In particular, a silicon wafer is utilized as a “platform” (interposer) upon which all of the components for a multiple number of transceiver modules are mounted or integrated, with the top surface of the silicon interposer used as a reference plane for defining the optical signal path between separate optical components. Indeed, by using a single silicon wafer as the platform for a large number of separate transceiver modules, one is able to use a wafer scale assembly process, as well as optical alignment and testing of these modules.

    Abstract translation: 光电子收发器组件过程的晶片级实现利用硅晶片作为光学参考平面和平台，同时为多个单独的收发器模块组装所有必需的光学和电子部件。 特别地，硅晶片被用作“平台”（插入器），在其上安装或集成多个收发器模块的所有组件，硅插入器的顶表面用作参考平面，用于定义 分离光学元件之间的光信号路径。 实际上，通过使用单个硅晶片作为大量单独的收发器模块的平台，可以使用晶片尺度组装过程以及这些模块的光学对准和测试。

    PHOTONIC CHIP WITH AN EVANESCENT COUPLING INTERFACE
    4.
    发明申请
    PHOTONIC CHIP WITH AN EVANESCENT COUPLING INTERFACE 审中-公开

    公开(公告)号：US20180188450A1

    公开(公告)日：2018-07-05

    申请号：US15899255

    申请日：2018-02-19

    Applicant: Cisco Technology, Inc.

    Inventor： Vipulkumar PATEL ,  Mark WEBSTER ,  Ravi TUMMIDI ,  Mary NADEAU

    IPC: G02B6/12 ,  G02B6/42 ,  G02B6/30 ,  G02B6/122

    Abstract: Embodiments herein describe a photonic chip which includes a coupling interface for evanescently coupling the chip to a waveguide on an external substrate. In one embodiment, the photonic chip includes a tapered waveguide that aligns with a tapered waveguide on the external substrate. The respective tapers of the two waveguides are inverted such that as the width of the waveguide in the photonic chip decreases, the width of the waveguide on the external substrate increases. In one embodiment, these two waveguides form an adiabatic structure where the optical signal transfers between the waveguides with minimal or no coupling of the optical signal to other non-intended modes. Using the two waveguides, optical signals can be transmitted between the photonic chip and the external substrate.

    ELECTRO-OPTICAL MODULATOR USING RIBBED WAVEGUIDES
    5.
    发明申请
    ELECTRO-OPTICAL MODULATOR USING RIBBED WAVEGUIDES 有权
    使用RIBBED WAVEGUIDES的电光调制器

    公开(公告)号：US20160170240A1

    公开(公告)日：2016-06-16

    申请号：US14248081

    申请日：2014-04-08

    Applicant: CISCO TECHNOLOGY , INC.

    Inventor： Donald ADAMS ,  Prakash GOTHOSKAR ,  Vipulkumar PATEL ,  Mark WEBSTER

    IPC: G02F1/025

    CPC classification number: G02F1/025 ,  G02B6/132 ,  G02B6/136 ,  G02F1/011 ,  G02F1/2257 ,  G02F2001/0152

    Abstract: An optical modulator may include a lower waveguide, an upper waveguide, and a dielectric layer disposed therebetween. When a voltage potential is created between the lower and upper waveguides, these layers form a silicon-insulator-silicon capacitor (also referred to as SISCAP) guide that provides efficient, high-speed optical modulation of an optical signal passing through the modulator. In one embodiment, at least one of the waveguides includes a respective ridge portion aligned at a charge modulation region which may aid in confining the optical mode laterally (e.g., in the width direction) in the optical modulator. In another embodiment, ridge portions may be formed on both the lower and the upper waveguides. These ridge portions may be aligned in a vertical direction (e.g., a thickness direction) so that ridges overlap which may further improve optical efficiency by centering an optical mode in the charge modulation region.

    Abstract translation: 光调制器可以包括下波导，上波导和介于其间的电介质层。 当在下波导和上波导之间产生电压电位时，这些层形成硅 - 绝缘体 - 硅电容器（也称为SISCAP）引导件，其提供通过调制器的光信号的有效的高速光调制。 在一个实施例中，至少一个波导包括在电荷调制区域处对准的相应的脊部分，其可以有助于限制光学调制器中的光学模式（例如，在宽度方向上）。 在另一个实施例中，脊部可以形成在下波导和上波导两者上。 这些脊部可以在垂直方向（例如，厚度方向）上对准，使得脊重叠，这可以通过使电荷调制区域中的光学模式居中来进一步提高光学效率。

    PHOTONIC INTEGRATION PLATFORM
    7.
    发明申请
    PHOTONIC INTEGRATION PLATFORM 审中-公开

    公开(公告)号：US20180341064A1

    公开(公告)日：2018-11-29

    申请号：US16052524

    申请日：2018-08-01

    Applicant: Cisco Technology, Inc.

    Inventor： Mark WEBSTER ,  Ravi Sekhar TUMMIDI

    IPC: G02B6/30 ,  G02B6/12 ,  G02B6/122 ,  G02B6/14 ,  G02B6/10 ,  G02B6/132 ,  G02B6/43

    Abstract: A SOI device may include a waveguide adapter that couples light between an external light source—e.g., a fiber optic cable or laser—and a silicon waveguide on the silicon surface layer of the SOI device. In one embodiment, the waveguide adapter is embedded into the insulator layer. Doing so may enable the waveguide adapter to be formed before the surface layer components are added onto the SOI device. Accordingly, fabrication techniques that use high-temperatures may be used without harming other components in the SOI device—e.g., the waveguide adapter is formed before heat-sensitive components are added to the silicon surface layer.

    MULTILAYER PHOTONIC ADAPTER
    10.
    发明申请
    MULTILAYER PHOTONIC ADAPTER 有权
    多层光电适配器

    公开(公告)号：US20160266321A1

    公开(公告)日：2016-09-15

    申请号：US14658220

    申请日：2015-03-15

    Applicant: Cisco Technology, Inc.

    Inventor： Ravi Sekhar TUMMIDI ,  Mark WEBSTER ,  Vipulkumar PATEL

    IPC: G02B6/30 ,  G02B6/10 ,  G02B6/122 ,  G02B6/12

    CPC classification number: G02B6/30 ,  G02B6/107 ,  G02B6/12004 ,  G02B6/122 ,  G02B6/1228 ,  G02B6/136 ,  G02B2006/12061 ,  G02B2006/121 ,  G02B2006/12142

    Abstract: Embodiments herein describe disposing a waveguide adapter onto an SOI device after the components on a silicon surface layer have been formed. That is, the waveguide adapter is disposed above optical components (e.g., optical modulators, detectors, waveguides, etc) formed in a surface layer. In one embodiment, a waveguide in a bottom layer of the waveguide adapter overlaps a silicon waveguide in the surface layer such that the silicon waveguide and the waveguide in the bottom layer are optically coupled. The waveguide adapter also includes other layers above the bottom layer (e.g., middle and top layers) that also contain waveguides which form an adiabatic optical system for transmitting an optical signal. At least one of the waveguides in the multi-layer adapter is exposed at an optical interface of the SOI device, thereby permitting the SOI device to transmit optical signals to, or receive optical signals from, an external optical component.

    Abstract translation: 本文的实施例描述了在形成硅表面层上的组分之后将波导适配器设置在SOI器件上。 也就是说，波导适配器设置在形成在表面层中的光学部件（例如，光学调制器，检测器，波导等）之上。 在一个实施例中，波导适配器的底层中的波导与表面层中的硅波导重叠，使得硅波导和底层中的波导光学耦合。 波导适配器还包括底层（例如，中层和顶层）之上的其它层，其也包含形成用于传输光信号的绝热光学系统的波导。 多层适配器中的至少一个波导在SOI器件的光学接口处露出，从而允许SOI器件将光信号传输到外部光学部件或从外部光学部件接收光信号。

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