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    PROCESS FOR FABRICATING WIRING BOARD
    5.
    发明申请
    PROCESS FOR FABRICATING WIRING BOARD 审中-公开
    制造布线板的工艺

    公开(公告)号：US20120174391A1

    公开(公告)日：2012-07-12

    申请号：US13423578

    申请日：2012-03-19

    申请人： Tsung-Yuan Chen ,  Chun-Chien Chen ,  Cheng-Po Yu

    发明人： Tsung-Yuan Chen ,  Chun-Chien Chen ,  Cheng-Po Yu

    IPC分类号： H05K3/00

    CPC分类号： H05K3/428 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/0038 ,  H05K3/20 ,  H05K3/205 ,  H05K2201/09509 ,  H05K2201/09563 ,  H05K2201/0969 ,  H05K2203/0369 ,  H05K2203/0376 ,  H05K2203/0384 ,  H05K2203/0554 ,  H05K2203/108 ,  H05K2203/1476 ,  Y10T29/49124 ,  Y10T29/49126

    摘要： A process for fabricating a wiring board is provided. In the process, a wiring carrying substrate including a carry substrate and a wiring layer is formed. Next, at least one blind via is formed in the wiring carrying substrate. Next, the wiring carrying substrate is laminated to another wiring carrying substrate via an insulation layer. The insulation layer is disposed between the wiring layers of the wiring carrying substrates and full fills the blind via. Next, parts of the carry substrates are removed to expose the insulation layer in the blind via. Next, a conductive pillar connected between the wiring layers is formed. Next, the rest carry substrates are removed.

    摘要翻译： 提供一种制造布线板的工艺。 在该过程中，形成包括携带衬底和布线层的布线承载衬底。 接下来，在布线承载基板中形成至少一个盲孔。 接下来，通过绝缘层将布线承载基板层叠到另一布线承载基板。 绝缘层设置在布线基板的布线层之间，并且完全填充盲孔。 接下来，去除部分搬运基板以露出盲孔中的绝缘层。 接下来，形成连接在布线层之间的导电柱。 接下来，其余的携带衬底被去除。

    Circuit structure and manufacturing method thereof
    6.
    发明授权
    Circuit structure and manufacturing method thereof 有权
    电路结构及其制造方法

    公开(公告)号：US08987608B2

    公开(公告)日：2015-03-24

    申请号：US13615722

    申请日：2012-09-14

    申请人： Shang-Feng Huang ,  Cheng-Po Yu ,  Jen-Chi Cheng

    发明人： Shang-Feng Huang ,  Cheng-Po Yu ,  Jen-Chi Cheng

    IPC分类号： H05K1/11 ,  H05K1/02 ,  H05K3/46

    CPC分类号： H05K1/0221 ,  H05K3/4644 ,  Y10T29/49155

    摘要： A circuit structure includes an inner circuit layer, a first and a second dielectric layers, a first and a second conductive material layers, and a second and a third conductive layers. The first dielectric layer covers a first conductive layer of the inner circuit layer and has a first surface and first circuit grooves. The first conductive material layer is disposed inside the first circuit grooves. The second conductive layer is disposed on the first surface and includes a signal trace and at least two reference traces. The second dielectric layer covers the first surface and the second conductive layer and has a second surface and second circuit grooves. Widths of the first and the second circuit grooves are smaller than that of the reference traces. The second conductive material layer is disposed inside the second circuit grooves. The third conductive layer is disposed on the second surface.

    摘要翻译： 电路结构包括内部电路层，第一和第二电介质层，第一和第二导电材料层以及第二和第三导电层。 第一电介质层覆盖内电路层的第一导电层，并具有第一表面和第一电路槽。 第一导电材料层设置在第一电路槽的内部。 第二导电层设置在第一表面上并且包括信号迹线和至少两个参考迹线。 第二电介质层覆盖第一表面和第二导电层，并具有第二表面和第二电路槽。 第一和第二电路槽的宽度小于参考轨迹的宽度。 第二导电材料层设置在第二电路槽的内部。 第三导电层设置在第二表面上。

    Embedded wiring board and method for manufacturing the same
    8.
    发明授权
    Embedded wiring board and method for manufacturing the same 有权
    嵌入式布线板及其制造方法

    公开(公告)号：US08373071B2

    公开(公告)日：2013-02-12

    申请号：US12696629

    申请日：2010-01-29

    申请人： Cheng-Po Yu ,  Chai-Liang Hsu

    发明人： Cheng-Po Yu ,  Chai-Liang Hsu

    IPC分类号： H05K1/00

    CPC分类号： H05K3/107 ,  H05K3/181 ,  H05K3/422 ,  H05K2201/0376

    摘要： A method for manufacturing an embedded wiring board is provided. An activating insulation layer is formed, in which the activating insulation layer includes a plurality of catalyst particles, and covers a first wiring layer. An intaglio pattern and at least one blind via partially exposing the first wiring layer are formed on the activating insulation layer, in which some of the catalyst particles are activated and exposed in the intaglio pattern and the blind via. The activating insulation layer is dipped in a first chemical plating solution, and a solid conductive pillar is formed in the blind via through electroless plating. The activating insulation layer is dipped in a second chemical plating solution after the solid conductive pillar is formed, and a second wiring layer is formed in the intaglio pattern through the electroless plating. Components of the first chemical plating solution and the second chemical plating solution are different.

    摘要翻译： 提供了一种用于制造嵌入式布线板的方法。 形成激活绝缘层，其中活化绝缘层包括多个催化剂颗粒，并覆盖第一布线层。 在活化绝缘层上形成凹版图案和部分露出第一布线层的至少一个盲孔，其中一些催化剂颗粒被活化并以凹版图案和盲孔曝光。 将激活绝缘层浸入第一化学镀溶液中，并通过化学镀在盲孔中形成固体导电柱。 在形成固体导电柱之后，将激活绝缘层浸入第二化学镀溶液中，并且通过无电解电镀在凹版图案中形成第二布线层。 第一化学镀液和第二化学镀液的成分不同。

    Method for forming embedded circuit
    9.
    发明授权
    Method for forming embedded circuit 失效
    嵌入式电路的形成方法

    公开(公告)号：US08171626B1

    公开(公告)日：2012-05-08

    申请号：US13155375

    申请日：2011-06-07

    申请人： Cheng-Po Yu ,  Chi-Min Chang

    发明人： Cheng-Po Yu ,  Chi-Min Chang

    IPC分类号： H05K3/02 ,  H05K3/10 ,  H05K3/00 ,  H01R9/00 ,  H01R43/00

    CPC分类号： H05K3/465 ,  H05K3/107 ,  H05K2201/0347 ,  Y10T29/49117 ,  Y10T29/49147 ,  Y10T29/49155

    摘要： A method for forming an embedded circuit is disclosed. First, a substrate including a dielectric layer is provided. Second, the dielectric layer is entirely covered by a dummy layer. Then, the dummy layer is patterned and a trench is formed in the dielectric layer at the same time. Later, a seed layer is formed to entirely cover the dummy layer and the trench. Next, the dummy layer is removed and the seed layer covering the dummy layer is removed, too. Afterwards, a metal layer is filled in the trench to form an embedded circuit embedded in the dielectric layer.

    摘要翻译： 公开了一种用于形成嵌入式电路的方法。 首先，提供包括电介质层的基板。 第二，介电层完全被虚拟层覆盖。 然后，对虚拟层进行图案化，同时在电介质层中形成沟槽。 之后，形成种子层以完全覆盖虚设层和沟槽。 接下来，去除虚拟层，并且去除覆盖虚拟层的种子层。 之后，在沟槽中填充金属层，形成嵌入电介质层的嵌入电路。

    CIRCUIT BOARD
    10.
    发明申请
    CIRCUIT BOARD 审中-公开
    电路板

    公开(公告)号：US20120031651A1

    公开(公告)日：2012-02-09

    申请号：US12944275

    申请日：2010-11-11

    申请人： TZYY-JANG TSENG ,  Chang-Ming Lee ,  Wen-Fang Liu ,  Cheng-Po Yu

    发明人： TZYY-JANG TSENG ,  Chang-Ming Lee ,  Wen-Fang Liu ,  Cheng-Po Yu

    IPC分类号： H05K1/02 ,  H05K1/18

    CPC分类号： H05K1/0203 ,  H05K1/056 ,  H05K3/3436 ,  H05K2201/0187 ,  H05K2201/10106

    摘要： A circuit board including a circuit layer, a thermally conductive substrate, an insulation layer, and at least one thermally conductive material is provided. The thermally conductive substrate has a plane. The insulation layer is disposed between the circuit layer and the plane and partially covers the plane. The thermally conductive material covers the plane without covered by the insulation layer and is in contact with the thermally conductive substrate. The insulation layer exposes the thermally conductive material.

    摘要翻译： 提供了包括电路层，导热基板，绝缘层和至少一种导热材料的电路板。 导热基板具有平面。 绝缘层设置在电路层和平面之间，并部分覆盖平面。 导热材料覆盖该平面而不被绝缘层覆盖，并与导热基板接触。 绝缘层暴露导热材料。