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公开(公告)号：US5272432A
公开(公告)日：1993-12-21
申请号：US691712
申请日：1991-05-01
申请人： Chinh D. Nguyen , Wei-Chan Hsu
发明人： Chinh D. Nguyen , Wei-Chan Hsu
CPC分类号： H03M1/0631 , H03M1/0863
摘要： In a digital-to-analog converter (DAC) current source including a current mirror, an output transistor biased by a reference voltage and a steering transistor, a structure and a method are provided to implement the DAC current source without current spikes in the output current. Current spikes in the output current are avoided by including a transistor acting as a low-pass filter between the steering transistor and the output transistor. In one embodiment, the DAC current source circuit is implemented by PMOS transistors.
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公开(公告)号：US5142219A
公开(公告)日：1992-08-25
申请号：US691710
申请日：1991-05-01
申请人： Wei-Chan Hsu , Chinh D. Nguyen , Fred T. Cheng
发明人： Wei-Chan Hsu , Chinh D. Nguyen , Fred T. Cheng
CPC分类号： H03F3/45192 , G05F1/575 , H03F2203/45028 , H03F2203/45182 , H03F2203/45244 , H03F2203/45478
摘要： A reference generator system that operates in either a current-controlled mode or a voltage-controlled mode and includes a power-down circuit connected to the operational amplifier to power down the operational amplifier when the reference generator is switched to the current-controlled mode.
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公开(公告)号：US5608369A
公开(公告)日：1997-03-04
申请号：US506465
申请日：1995-07-25
CPC分类号： H01F7/1607 , F02M51/04 , F02M57/027 , F02M59/462 , F02M59/464 , F02M61/08
摘要： A method of constructing a magnetic flux gap comprising fabricating a first portion from a material having low reluctance and so as to provide an end surface, and a cylindrical inner surface having a diameter, fabricating a second portion from a material having high reluctance and so as to provide axially spaced first and second end surfaces, and a cylindrical inner surface having a diameter greater than the diameter of said cylindrical inner surface of said first portion, fabricating a third portion from a material having low reluctance and so as to provide an end surface, and a cylindrical inner surface having a diameter substantially equal to the diameter of said cylindrical inner surface of said first portion, fixing together the first and second portions with the first end surface of the second portion in axially abutting adjacent relation to the end surface of the first portion and with said cylindrical inner surfaces in concentric relation, fixing together the second and third portions with the second end surface of the second portion in axially abutting adjacent relation to the end surface of the third portion and with said cylindrical inner surfaces in concentric relation, whereby to define a magnetic flux gap radially inwardly of the cylindrical surface of the second portion.
摘要翻译： 一种构造磁通量间隙的方法，包括从具有低磁阻的材料制造第一部分并提供端面，以及具有直径的圆柱形内表面，从具有高磁阻的材料制造第二部分，并且如 以提供轴向间隔开的第一和第二端面，以及圆柱形内表面，其直径大于所述第一部分的所述圆柱形内表面的直径，从具有低磁阻的材料制造第三部分，并且提供端面 以及圆柱形内表面，其直径基本上等于所述第一部分的所述圆柱形内表面的直径，将第一和第二部分与第二部分的第一端面固定在一起，与第二部分的第一端面相对于 第一部分和与所述圆柱形内表面同心的关系，固定在一起的第二和第三p 所述第二部分的第二端表面与所述第三部分的端面轴向邻接，并且所述圆柱形内表面具有同心的关系，从而限定第二部分的圆柱形表面径向向内的磁通量隙 。
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公开(公告)号：US5982693A
公开(公告)日：1999-11-09
申请号：US987796
申请日：1997-12-10
申请人： Chinh D. Nguyen
发明人： Chinh D. Nguyen
CPC分类号： G11C7/062
摘要： A semiconductor memory includes cell array having a plurality of bit lines connected to respective input terminals of a column decoder. Input/output (I/O) lines are connected between respective output terminals of the column decoder and a plurality of sense circuits, where each sense circuit includes its own reference circuit, a sense amplifier, and equalizing circuit. The reference circuit includes a reference array essentially identical to the cell array and provides a reference voltage to respective first input terminals of its associated equalizing circuit and sense amplifier. Second input terminals of the equalizing circuit and sense amplifier of each sense circuit are connected to a corresponding I/O line. During read operations, the equalizing circuits are initially maintained in a conductive state so as to equalize the I/O line voltage and the reference voltages. Thereafter, the equalizing circuits transition to a non-conductive state so as to isolate the I/O line from the reference voltage. In response thereto, each I/O line voltage immediately changes to either a more positive or more negative voltage, depending on the binary state of the cell associated therewith.
摘要翻译： 半导体存储器包括具有连接到列解码器的相应输入端的多个位线的单元阵列。 输入/输出（I / O）线连接在列解码器的各个输出端和多个检测电路之间，其中每个检测电路包括其自己的参考电路，读出放大器和均衡电路。 参考电路包括基本上与单元阵列相同的参考阵列，并将参考电压提供给其相关联的均衡电路和读出放大器的相应的第一输入端。 每个感测电路的均衡电路和读出放大器的第二输入端子连接到相应的I / O线。 在读取操作期间，均衡电路最初保持在导通状态，以便使I / O线电压和参考电压相等。 此后，均衡电路转换到非导通状态，以将I / O线与参考电压隔离。 响应于此，取决于与其相关联的单元的二进制状态，每个I / O线电压立即变为更正或更负的电压。
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公开(公告)号：US5943268A
公开(公告)日：1999-08-24
申请号：US001401
申请日：1997-12-31
申请人： Chinh D. Nguyen
发明人： Chinh D. Nguyen
IPC分类号： G11C16/04
CPC分类号： G11C16/0441
摘要： A non-volatile latch is disclosed which includes four PMOS floating gate memory cells arranged in a 2.times.2 matrix. Binary data values are written to the latch by the threshold voltage of the cells, where a first binary value is written by programming all the cells, and the second binary value is written by leaving all the cells in an erased state. Thus, since a program operation is required when writing only one of the binary value, high program voltages and floating gate charge times are eliminated when writing the other binary value. After a read operation in which the binary value stored in the cells is provided as output, this binary value is automatically latched in a latch circuit. In this manner, subsequent reads to the latch do not require accessing the cells.
摘要翻译： 公开了一种非易失性锁存器，其包括以2x2矩阵布置的四个PMOS浮栅存储器单元。 二进制数据值通过单元的阈值电压写入锁存器，其中通过对所有单元进行编程来写入第一二进制值，并且通过将所有单元格保留为擦除状态来写入第二二进制值。 因此，由于在仅写入二进制值中的一个时需要编程操作，所以在写入其他二进制值时，消除了高编程电压和浮置栅极充电时间。 在将存储在单元中的二进制值提供为输出的读操作之后，该二进制值被自动锁存在锁存电路中。 以这种方式，对锁存器的后续读取不需要访问单元。
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公开(公告)号：US5801994A
公开(公告)日：1998-09-01
申请号：US911968
申请日：1997-08-15
申请人： Shang-De Ted Chang , Chinh D. Nguyen , Guy S. Yuen
发明人： Shang-De Ted Chang , Chinh D. Nguyen , Guy S. Yuen
IPC分类号： G11C16/04
CPC分类号： G11C16/0416
摘要： A memory array includes a predetermined number of rows of PMOS Flash memory cells formed in each of a plurality of n- well regions of a semiconductor substrate, where each of the n- well regions defines a page of the memory array. In some embodiments, a plurality of bit lines define columns of the memory array, where the p+ drain of each of the memory cells in a common column are coupled to an associated one of the bit lines. In other embodiments, a plurality of sub-bit lines define columns of the memory array, where the p+ drain of each of the memory cells in a common column are coupled to an associated one of the sub-bit lines, and groups of a predetermined number of the sub-bit lines are selectively coupled to associated ones of a plurality of bit lines via pass transistors. During erasing operations a selected n- well region, within which are formed the memory cells of a selected page, is held at a first voltage, while the other n- well regions, within which are formed the memory cells of the respective un-selected pages, are held at a second voltage. The first and second voltages are different, thereby isolating the un-selected pages from erasing operations of the selected page.
摘要翻译： 存储器阵列包括形成在半导体衬底的多个n阱区域中的每一个中的预定数量的PMOS闪存单元行，其中n阱区域中的每一个限定存储器阵列的页面。 在一些实施例中，多个位线限定存储器阵列的列，其中公共列中的每个存储器单元的p +漏极耦合到相关联的一个位线。 在其他实施例中，多个子位线定义存储器阵列的列，其中公共列中的每个存储器单元的p +漏极耦合到相关联的一个子位线，以及预定的 子位线的数量通过传输晶体管选择性地耦合到多个位线中的相关联的位线。 在擦除操作期间，形成所选页面的存储单元的选定n阱区域被保持在第一电压，而在其中形成相应未选择的存储单元的其它n-阱区域 页面被保持在第二电压。 第一和第二电压是不同的，从而将未选择的页面与所选页面的擦除操作隔离。
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公开(公告)号：US5909392A
公开(公告)日：1999-06-01
申请号：US948531
申请日：1997-10-09
CPC分类号： G11C16/3409 , G11C16/0483 , G11C16/3404
摘要： A nonvolatile PMOS memory array includes a plurality of pages, where each column of a page includes two series-connected PMOS OR strings in parallel with a bit line. Each PMOS OR string includes a PMOS select transistor coupled between the bit line and two series connected PMOS floating gate memory cells. The PMOS floating gate memory cells are programmed via channel hot electron (CHE) injection and erased via electron tunneling. A soft-program mechanism is used to compensate for over-erasing of the memory cells. In some embodiments, the bit lines are segmented along page boundaries to increase speed.
摘要翻译： 非易失性PMOS存储器阵列包括多页，其中页的每列包括与位线并联的两个串联连接的PMOS或字符串。 每个PMOS或串包括耦合在位线和两个串联连接的PMOS浮栅存储器单元之间的PMOS选择晶体管。 PMOS浮栅存储单元通过通道热电子（CHE）注入进行编程，并通过电子隧道擦除。 软程序机制用于补偿存储器单元的过度擦除。 在一些实施例中，位线沿着页边界被分段以增加速度。
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公开(公告)号：US5638011A
公开(公告)日：1997-06-10
申请号：US694958
申请日：1996-08-08
申请人： Chinh D. Nguyen
发明人： Chinh D. Nguyen
IPC分类号： H03K17/041 , H03K17/16 , H03M1/74 , H03K3/00
CPC分类号： H03M1/742 , H03K17/04106 , H03K17/162
摘要： Arrangement for providing improved current source signals in a DAC current source circuit including a current source transistor, an output transistor, and a switching transistor for selectively grounding the source current or directing it through the output transistor. The DAC current source circuit includes a high gain double cascode device for electrically isolating the current source and output transistors from the switching transistor. The isolation device may include one, two or more transistors in series. The arrangement further includes a matching circuit at the input of the DAC current source circuit.
摘要翻译： 用于在包括电流源晶体管，输出晶体管和开关晶体管的DAC电流源电路中提供改进的电流源信号的布置，用于选择性地将源极接地或将其引导通过输出晶体管。 DAC电流源电路包括用于将电流源和输出晶体管与开关晶体管电隔离的高增益双共射共栅器件。 隔离装置可以包括一个，两个或更多个串联的晶体管。 该装置还包括在DAC电流源电路的输入处的匹配电路。
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9.发明授权Method and apparatus for switching a well potential in response to an output voltage 失效响应于输出电压来切换阱电位的方法和装置公开(公告)号：US06204721B1
公开(公告)日：2001-03-20
申请号：US09082485
申请日：1998-05-20
申请人： Guy S. Yuen , Chinh D. Nguyen
发明人： Guy S. Yuen , Chinh D. Nguyen
IPC分类号： H03K031
CPC分类号： H02M3/07
摘要： A switching circuit includes a switch having first and second terminals coupled between a voltage supply and ground potential and having a control terminal coupled to receive a control signal indicative of the output voltage of an associated semiconductor circuit. The switch also includes an output terminal coupled to the well region within which is formed the associated semiconductor circuit. In preferred embodiments, the control signal transitions from a first state to a second state when the output voltage exceeds a predetermined potential. In response thereto, the switching circuit changes the well potential of the associated semiconductor circuit from a first voltage to ground potential, wherein the first voltage is greater than ground potential.
摘要翻译： 开关电路包括具有耦合在电压源和接地电位之间的第一和第二端子的开关，并且具有耦合以接收指示相关半导体电路的输出电压的控制信号的控制端子。 开关还包括耦合到阱区的输出端，在该区内形成相关联的半导体电路。 在优选实施例中，当输出电压超过预定电位时，控制信号从第一状态转变到第二状态。 响应于此，开关电路将相关联的半导体电路的阱电势从第一电压改变到接地电位，其中第一电压大于地电位。
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公开(公告)号：US5973967A
公开(公告)日：1999-10-26
申请号：US985561
申请日：1997-12-05
摘要： A page buffer facilitates programming of a memory cell within an associated memory array by selectively connecting a bit line associated with the memory cell to a negative voltage supply in response to the logic state of a data signal. The page buffer includes an SRAM latch having first and second nodes, a cross-coupled latch having first and second nodes, and a pass transistor. The first node of the SRAM latch is coupled to receive the data signal and to a first control terminal of the cross-coupled latch. The second node of the SRAM latch is coupled to a second control terminal of the cross-coupled latch. The second node of the cross-coupled latch is coupled to a gate of the pass transistor which, in turn, is connected between the bit line and the negative voltage supply. When the data signal is in a first logic state, the cross-coupled latch turns on the pass transistor and, in connecting the bit line to the negative voltage supply, facilitates programming of the cell. When the data signal is in a second logic state, the cross-coupled latch turns off the pass transistor and allows the bit line to float which, in turn, precludes programming of the cell.
摘要翻译： 页面缓冲器通过响应于数据信号的逻辑状态选择性地将与存储器单元相关联的位线选择性地连接到负电压源来便于对相关存储器阵列内的存储器单元进行编程。 页缓冲器包括具有第一和第二节点的SRAM锁存器，具有第一和第二节点的交叉耦合锁存器和传输晶体管。 SRAM锁存器的第一节点被耦合以接收数据信号和交叉耦合锁存器的第一控制端。 SRAM锁存器的第二节点耦合到交叉耦合锁存器的第二控制端。 交叉耦合锁存器的第二个节点耦合到传输晶体管的栅极，该栅极又连接在位线和负电压源之间。 当数据信号处于第一逻辑状态时，交叉耦合的锁存器导通传输晶体管，并且在将位线连接到负电压源时便于对单元进行编程。 当数据信号处于第二逻辑状态时，交叉耦合的锁存器关闭传输晶体管，并允许位线浮动，这反过来妨碍了单元的编程。
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