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    Pixel circuit, display panel and display apparatus
    2.
    发明授权
    Pixel circuit, display panel and display apparatus 有权
    像素电路，显示面板和显示设备

    公开(公告)号：US09251737B2

    公开(公告)日：2016-02-02

    申请号：US14382506

    申请日：2013-12-05

    Applicant: BOE TECHNOLOGY GROUP CO., LTD.

    Inventor： Liang Sun ,  Jang Soon Im ,  Lujiang Huangfu

    IPC: G09G3/32 ,  G09G5/10

    CPC classification number: G09G3/3291 ,  G09G3/3208 ,  G09G3/3233 ,  G09G3/3258 ,  G09G5/10 ,  G09G2300/0426 ,  G09G2300/0819 ,  G09G2300/0842 ,  G09G2320/0223 ,  G09G2320/0233 ,  G09G2330/028

    Abstract: A pixel circuit, display panel and display apparatus are provided. The pixel circuit comprises a driving sub-circuit, whose first terminal is connected with first reference voltage source via power supply lead, and second terminal is connected with first terminal of a light emitting device; a charging sub-circuit, whose output terminal is connected with third terminal of the driving sub-circuit, which is configured to charge the driving sub-circuit before the driving sub-circuit drives the light emitting device to emit light; and a compensation sub-circuit, whose first terminal is connected with second terminal of the light emitting device, second terminal is connected with second reference voltage source, which is configured to compensate for voltage drop on the power supply lead of voltage which is provided to the driving sub-circuit from the first reference voltage source, so as to raise the uniformity of display brightness within display area of the panel.

    Abstract translation: 提供像素电路，显示面板和显示装置。 像素电路包括驱动子电路，其第一端子经由电源引线与第一参考电压源连接，第二端子与发光器件的第一端子连接; 充电子电路，其输出端子与驱动子电路的第三端子连接，其被配置为在驱动子电路驱动发光器件发光之前对驱动子电路充电; 以及补偿子电路，其第一端子与发光器件的第二端子连接，第二端子与第二参考电压源连接，第二参考电压源被配置为补偿电源引线上的电压降，其被提供给 来自第一参考电压源的驱动子电路，以便提高面板显示区域内的显示亮度的均匀性。

    Array substrate and manufacturing method thereof, display device
    5.
    发明授权
    Array substrate and manufacturing method thereof, display device 有权
    阵列基板及其制造方法，显示装置

    公开(公告)号：US09449995B2

    公开(公告)日：2016-09-20

    申请号：US14416358

    申请日：2014-05-13

    Applicant: BOE TECHNOLOGY GROUP CO., LTD.

    Inventor： Jang Soon Im

    IPC: H01L21/00 ,  H01L27/12

    CPC classification number: H01L27/1251 ,  H01L27/1222 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1259 ,  H01L27/127

    Abstract: An array substrate and manufacturing method thereof and a display device are provided. The array substrate comprises a substrate (10) and a plurality of complementary thin film transistors provided on the substrate (10). The plurality of complementary thin film transistors comprise a first N-type thin film transistor (11) and a second P-type thin film transistor (12), and the first thin film transistor (11) is an oxide thin film transistor and the second thin film transistor (12) is a poly-silicon thin film transistor. The method of manufacturing the array substrate simplifies the manufacturing process and reduces production difficulty and cost.

    Abstract translation: 提供阵列基板及其制造方法和显示装置。 阵列基板包括衬底（10）和设置在衬底（10）上的多个互补薄膜晶体管。 多个互补薄膜晶体管包括第一N型薄膜晶体管（11）和第二P型薄膜晶体管（12），第一薄膜晶体管（11）是氧化物薄膜晶体管，第二薄膜晶体管 薄膜晶体管（12）是多晶硅薄膜晶体管。 阵列基板的制造方法简化了制造工序，降低了生产难度和成本。

    Complementary metal oxide semiconductor circuit structure, preparation method thereof and display device
    7.
    发明授权
    Complementary metal oxide semiconductor circuit structure, preparation method thereof and display device 有权
    互补金属氧化物半导体电路结构及其制备方法和显示装置

    公开(公告)号：US09147772B2

    公开(公告)日：2015-09-29

    申请号：US14103175

    申请日：2013-12-11

    Applicant: BOE TECHNOLOGY GROUP CO., LTD.

    Inventor： Jang Soon Im

    IPC: H01L29/10 ,  H01L29/786 ,  H01L27/12

    CPC classification number: H01L29/7869 ,  H01L27/1225 ,  H01L27/1251

    Abstract: Provided are a CMOS circuit structure, a preparation method thereof and a display device, wherein a PMOS region in the CMOS circuit structure is of a LTPS TFT structure, that is, the PMOS semiconductor layer is prepared from a P type doped polysilicon material; an NMOS region is of an Oxide TFT structure, that is, the NMOS semiconductor layer is made of an oxide material; three doping processes applied to the NMOS region during the LTPS process may be omitted in the case in which the NMOS semiconductor layer in the NMOS region is made of an oxide material instead of the polysilicon material, which may simplify the preparation of the CMOS circuit structure as well as reduce a production cost. Furthermore, it is only required to crystallizing the PMOS semiconductor layer, which may also extend the lifespan of laser tube, contributing to reduction of the production cost.

    Abstract translation: 提供了一种CMOS电路结构，其制备方法和显示装置，其中CMOS电路结构中的PMOS区域是LTPS TFT结构，即PMOS半导体层由P型掺杂多晶硅材料制备; NMOS区域是氧化物TFT结构，即NMOS半导体层由氧化物材料制成; 在NMOS区域中的NMOS半导体层由氧化物材料代替多晶硅材料制成的情况下，可以省略在LTPS工艺期间施加到NMOS区域的三种掺杂工艺，这可以简化CMOS电路结构的制备 并降低生产成本。 此外，仅需要使PMOS半导体层结晶，这也可能延长激光管的寿命，有助于降低生产成本。

    Array substrate and manufacturing method thereof, display device, thin film transistor and manufacturing method thereof
    9.
    发明授权
    Array substrate and manufacturing method thereof, display device, thin film transistor and manufacturing method thereof 有权
    阵列基板及其制造方法，显示装置，薄膜​​晶体管及其制造方法

    公开(公告)号：US09478562B2

    公开(公告)日：2016-10-25

    申请号：US14646416

    申请日：2014-09-23

    Applicant: BOE TECHNOLOGY GROUP CO., LTD.

    Inventor： Chunping Long ,  Zheng Liu ,  Zuqiang Wang ,  Jang Soon Im

    IPC: H01L21/00 ,  H01L27/12 ,  H01L29/66 ,  H01L29/786 ,  H01L27/32

    CPC classification number: H01L27/1222 ,  H01L21/77 ,  H01L27/12 ,  H01L27/1214 ,  H01L27/1218 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/1255 ,  H01L27/1274 ,  H01L27/1288 ,  H01L27/3246 ,  H01L27/3248 ,  H01L27/3262 ,  H01L27/3265 ,  H01L29/66757 ,  H01L29/78675 ,  H01L2227/323

    Abstract: An array substrate and manufacturing method thereof, a display device, a thin film transistor and manufacturing method thereof are provided. The manufacturing method of an array substrate includes forming an active material layer (501), a gate insulating layer (204) and a metal thin film (502) on a base substrate (201), and forming a pattern including an active layer (203) and a pattern including a gate electrode (205), a source electrode (206), a drain electrode (207), a gate line (1063) and a data line (1061) by a first patterning process; forming a passivation layer (301) on the base substrate (201), and forming a source contact hole (302), a drain contact hole (303), and an bridge-structure contact hole (1062a) by a second patterning process; forming a transparent conductive thin film (1401) on the base substrate (201), and removing the transparent conductive thin film (1404) partially, so that a source contact section (401), a drain contact section (402), a pixel electrode (403), and an bridge structure (1062) are formed. With the manufacturing method, the use number of patterning processes is decreased.

    Abstract translation: 提供阵列基板及其制造方法，显示装置，薄膜​​晶体管及其制造方法。 阵列基板的制造方法包括在基底基板（201）上形成活性物质层（501），栅极绝缘层（204）和金属薄膜（502），形成包括活性层（203）的图案 ）和通过第一图案化工艺包括栅电极（205），源电极（206），漏电极（207），栅线（1063）和数据线（1061）的图案; 在所述基底基板上形成钝化层，通过第二构图工艺形成源极接触孔，漏极接触孔和桥接结构接触孔; 在所述基底基板上形成透明导电薄膜，将所述透明导电薄膜部分地去除，使得源极接触部分，漏极接触部分，像素电极， （403）和桥结构（1062）。 通过制造方法，图案化处理的使用次数减少。

    THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREOF, ARRAY SUBSTRATE AND DISPLAY DEVICE
    10.
    发明申请
    THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREOF, ARRAY SUBSTRATE AND DISPLAY DEVICE 审中-公开
    薄膜晶体管及其制造方法，阵列基板和显示器件

    公开(公告)号：US20150171224A1

    公开(公告)日：2015-06-18

    申请号：US14124104

    申请日：2012-12-06

    Applicant: BOE TECHNOLOGY GROUP CO., LTD.

    Inventor： Zheng Liu ,  Chunping Long ,  Jang Soon Im

    IPC: H01L29/786 ,  H01L27/12

    CPC classification number: H01L29/78606 ,  H01L27/1248 ,  H01L29/41733 ,  H01L29/6675

    Abstract: Embodiments of the present invention relate to display technology field and provide a thin film transistor (1) and manufacturing method thereof, an array substrate, and a display device, and do not damage an active layer (12) of the thin film transistor while forming vias (16) over the source region (120) and the drain region (121) with via etching process. The thin film transistor (1) comprises a substrate (10), an active layer (12), a gate insulating layer (13), a gate (14) and an inter-layer insulating layer (17) disposed on the substrate (10), and further comprises: a conductive etching barrier layer (15) disposed on the active layer; the conductive etching barrier layer (15) being located to correspond to the source region (120) and the drain region (121) of the active layer (12) and vias (16) being formed over the source region (120) and the drain region (121) of the active layer (12) and not extending beyond edges of the conductive etching barrier layer (15).

    Abstract translation: 本发明的实施例涉及显示技术领域并提供薄膜晶体管（1）及其制造方法，阵列基板和显示装置，并且不会在形成时损坏薄膜晶体管的有源层（12） 通过蚀刻工艺在源区（120）和漏区（121）之间的通路（16）。 薄膜晶体管（1）包括基板（10），有源层（12），栅极绝缘层（13），栅极（14）和布置在基板（10）上的层间绝缘层 ），还包括：设置在所述有源层上的导电蚀刻阻挡层（15） 所述导电蚀刻阻挡层（15）被定位成对应于有源层（12）的源极区域（120）和漏极区域（121）以及形成在源极区域（120）和漏极 （12）的区域（121），并且不延伸超过导电蚀刻阻挡层（15）的边缘。

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