公开(公告)号：US20140264354A1

公开(公告)日：2014-09-18

申请号：US14203433

申请日：2014-03-10

Applicant: APPLIED MATERIALS, INC.

Inventor： Kurtis LESCHKIES ,  Steven VERHAVERBEKE ,  Robert VISSER ,  John M. WHITE ,  Yan YE ,  Dong-Kil YIM

IPC: H01L29/786

CPC classification number: H01L29/7869 ,  H01L29/4908

Abstract: The present invention generally relates to a thin film semiconductor device having a buffer layer formed between the semiconductor layer and one or more layers. In one embodiment, a thin film semiconductor device includes a semiconductor layer having a first work function and a first electron affinity level, a buffer layer having a second work function greater than the first work function and a second electron affinity level that is less than the first electron affinity level; and a gate dielectric layer having a third work function less than the second work function and a third electron affinity level that is greater than the second electron affinity level.

Abstract translation: 本发明一般涉及一种在半导体层与一层或多层之间形成缓冲层的薄膜半导体器件。 在一个实施例中，薄膜半导体器件包括具有第一功函数和第一电子亲和度的半导体层，具有大于第一功函数的第二功函数的缓冲层和小于第一功函数的第二电子亲和度 第一电子亲和力水平; 以及具有小于第二功函数的第三功函数和大于第二电子亲和度的第三电子亲和度的栅介质层。

公开(公告)号：US20200083052A1

公开(公告)日：2020-03-12

申请号：US16685074

申请日：2019-11-15

Applicant: Applied Materials, Inc.

Inventor： Yujia ZHAI ,  Xiangxin RUI ,  Lai ZHAO ,  Dong-Kil YIM ,  Soo Young CHOI

IPC: H01L21/28 ,  H01L21/02 ,  H01L29/423 ,  H01L49/02 ,  H01L29/78 ,  H01L29/51

Abstract: Embodiments of the disclosure generally relate to a layer stack containing a dielectric layer having a high K value capable of improving semiconductor display device electrical performance. The layer stack includes a channel layer containing an amorphous silicon layer disposed on a substrate and a gate insulating layer disposed on the channel layer. The gate insulating layer contains a silicon dioxide layer disposed on the channel layer, a zirconium dioxide layer disposed on the silicon dioxide layer, and an interface layer disposed on the zirconium dioxide layer and containing titanium oxide or aluminum oxide. The zirconium dioxide layer is disposed between the silicon dioxide layer and the interface layer and has a thickness of about 250 Å or greater, the gate insulating layer has a K value of about 20 to about 50, and the silicon dioxide layer is disposed between the channel layer and the zirconium dioxide layer.

公开(公告)号：US20170012064A1

公开(公告)日：2017-01-12

申请号：US15202070

申请日：2016-07-05

Applicant: Applied Materials, Inc.

Inventor： Soo Young CHOI ,  Tae Kyung WON ,  Dong-Kil YIM ,  Yi CUI ,  Xuena ZHANG

IPC: H01L27/12

CPC classification number: H01L27/1248 ,  H01L27/3262

Abstract: Embodiments of the present disclosure generally relate to methods and devices for use of low temperature polysilicon (LTPS) thin film transistors in liquid crystal display (LCD) and organic light-emitting diode (OLED) displays.

Abstract translation: 本公开的实施例一般涉及在液晶显示器（LCD）和有机发光二极管（OLED）显示器中使用低温多晶硅（LTPS）薄膜晶体管的方法和装置。

公开(公告)号：US20140216929A1

公开(公告)日：2014-08-07

申请号：US14169203

申请日：2014-01-31

Applicant: Applied Materials, Inc.

Inventor： Aki HOSOKAWA ,  John M. WHITE ,  Dong-Kil YIM

IPC: C23C14/34

CPC classification number: C23C14/3414 ,  C23C14/08 ,  C23C14/3407

Abstract: The present invention generally relates to a sputtering target comprised of zinc and a dopant. Zinc is utilized for metal oxide semiconductor materials, such as IGZO, zinc oxide and zinc oxynitride. The zinc may be delivered by sputtering a zinc target in a desired atmosphere. If a pure zinc sputtering target is used, a stable film cannot be produced unless mobility is sacrificed to below 10 cm2/V-s. By adding a dopant, such as gallium, not only can a stable film be deposited, but the film will have a mobility of greater than 30 cm2/V-s. The dopant can be incorporated directly into the zinc or as a separate sputtering target directly adjacent the zinc sputtering target.

Abstract translation: 本发明一般涉及由锌和掺杂剂组成的溅射靶。 锌用于金属氧化物半导体材料，例如IGZO，氧化锌和氮氧化锌。 可以通过在期望的气氛中溅射锌靶来递送锌。 如果使用纯锌溅射靶，则不能产生稳定的膜，除非将迁移率降低至10cm 2 / V-s以下。 通过添加诸如镓的掺杂剂，不仅可以沉积稳定的膜，而且膜将具有大于30cm 2 / V-s的迁移率。 掺杂剂可以直接结合到锌中或作为与锌溅射靶直接相邻的单独的溅射靶。

公开(公告)号：US20210043757A1

公开(公告)日：2021-02-11

申请号：US17082570

申请日：2020-10-28

Applicant: Applied Materials, Inc.

Inventor： Soo Young CHOI ,  Beom Soo PARK ,  Yi CUI ,  Tae Kyung WON ,  Dong-Kil YIM

IPC: H01L29/66 ,  H01L29/786 ,  H01L21/02 ,  H01L23/31

Abstract: Techniques are disclosed for methods of post-treating an etch stop or a passivation layer in a thin film transistor to increase the stability behavior of the thin film transistor.

公开(公告)号：US20180345330A1

公开(公告)日：2018-12-06

申请号：US16007876

申请日：2018-06-13

Applicant: Applied Materials, Inc.

Inventor： Yujia ZHAI ,  Lai ZHAO ,  Xiangxin RUI ,  Dong-Kil YIM ,  Tae Kyung WON ,  Soo Young CHOI

IPC: B08B7/00 ,  H01J37/32 ,  B08B9/00 ,  C23C16/44

Abstract: In one implementation, a method for cleaning a processing chamber is provided. The method comprises introducing a reactive species into a processing chamber having a residual high-k dielectric material formed on one or more interior surfaces of the processing chamber. The reactive species is formed from a halogen-containing gas mixture and the one or more interior surfaces include at least one surface having a coating material formed thereon. The method further comprises reacting the residual high-k dielectric material with the reactive species to form a volatile product. The method further comprises removing the volatile product from the processing chamber. The removal rate of the residual high-k dielectric material is greater than a removal rate of the coating material. The high-k dielectric material is selected from zirconium dioxide (ZrO2) and hafnium dioxide (HfO2). The coating material includes a compound selected from alumina (Al2O3), yttrium-containing compounds, and combinations thereof.

公开(公告)号：US20170162678A1

公开(公告)日：2017-06-08

申请号：US15412545

申请日：2017-01-23

Applicant: Applied Materials, Inc.

Inventor： Dong-Kil YIM ,  Tae Kyung WON ,  Seon-Mee CHO ,  John M. WHITE

IPC: H01L29/66 ,  H01L21/467 ,  H01L29/24 ,  H01L29/786

CPC classification number: H01L29/66969 ,  H01L21/467 ,  H01L29/24 ,  H01L29/78603 ,  H01L29/78606 ,  H01L29/7869

Abstract: The present invention generally relates to TFTs and methods for fabricating TFTs. For either back channel etch TFTs or for etch stop TFTs, multiple layers for the passivation layer or the etch stop layers permits a very dense capping layer to be formed over a less dense back channel protection layer. The capping layer can be sufficiently dense so that few pin holes are present and thus, hydrogen may not pass through to the semiconductor layer. As such, hydrogen containing precursors may be used for the capping layer deposition.

公开(公告)号：US20140273342A1

公开(公告)日：2014-09-18

申请号：US14201532

申请日：2014-03-07

Applicant: Applied Materials, Inc.

Inventor： Dong-Kil YIM ,  Rodney Shunleong LIM ,  Evelyn SCHEER ,  Tae Kyung WON ,  Soo Young CHOI ,  Harvey YOU

IPC: H01L29/66

CPC classification number: H01L29/66742 ,  H01L29/66969 ,  H01L29/7869

Abstract: The present invention generally relates to TFTs and methods for fabricating TFTs. When multiple layers are used for the semiconductor material in a TFT, a negative Vth shift may result. By exposing the semiconductor layer to an oxygen containing plasma and/or forming an etch stop layer thereover, the negative Vth shift may be negated.

Abstract translation: 本发明一般涉及TFT和TFT的制造方法。 当TFT中的半导体材料使用多层时，可能产生负的Vth偏移。 通过将半导体层暴露于含氧等离子体和/或在其上形成蚀刻停止层，可以否定负的Vth偏移。

公开(公告)号：US20190206691A1

公开(公告)日：2019-07-04

申请号：US15862522

申请日：2018-01-04

Applicant: Applied Materials, Inc.

Inventor： Yujia ZHAI ,  Xiangxin RUI ,  Lai ZHAO ,  Dong-Kil YIM ,  Soo Young CHOI

IPC: H01L21/28 ,  H01L21/02 ,  H01L29/423 ,  H01L49/02 ,  H01L29/51 ,  H01L29/78

CPC classification number: H01L21/28167 ,  H01L21/02148 ,  H01L21/3105 ,  H01L21/76843 ,  H01L28/56 ,  H01L29/42364 ,  H01L29/513 ,  H01L29/517 ,  H01L29/78

Abstract: Embodiments of the present disclosure generally relate to a layer stack including a dielectric layer having a high K value capable of improving semiconductor display device electrical performance. In one embodiment, the layer stack includes a substrate, a channel layer disposed on the substrate, and a gate insulating layer. The gate insulating layer includes an interface layer disposed on the channel layer and a zirconium dioxide layer disposed on the interface layer. The gate insulating layer has a K value ranging from about 20 to about 50. The high k value of the gate insulating layer reduces the subthreshold swing (SS) causing a higher energy barrier which alleviates the short channel effect and leakage in display devices. Additionally, the high k value of the gate insulating layer enables for a faster driving current that improves brightness and performance of the display device.

公开(公告)号：US20180145157A1

公开(公告)日：2018-05-24

申请号：US15874081

申请日：2018-01-18

Applicant: Applied Materials, Inc.

Inventor： Soo Young CHOI ,  Beom Soo PARK ,  Yi CUI ,  Tae Kyung WON ,  Dong-Kil YIM

IPC: H01L29/66 ,  H01L29/786 ,  H01L21/02 ,  H01L23/31

CPC classification number: H01L29/66969 ,  H01L21/0234 ,  H01L23/3171 ,  H01L29/7869 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Techniques are disclosed for methods of post-treating an etch stop or a passivation layer in a thin film transistor to increase the stability behavior of the thin film transistor.