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公开(公告)号:US20230282498A1
公开(公告)日:2023-09-07
申请号:US18195234
申请日:2023-05-09
Applicant: Applied Materials, Inc.
Inventor: Kurtis LESCHKIES , Jeffrey L. FRANKLIN , Wei-Sheng LEI , Steven VERHAVERBEKE , Jean DELMAS , Han-Wen CHEN , Giback PARK
IPC: H01L21/67 , H01L21/48 , B23K26/0622 , B23K26/382
CPC classification number: H01L21/67121 , H01L21/486 , B23K26/0622 , B23K26/382 , H01L23/49827
Abstract: The present disclosure relates to systems and methods for fabricating semiconductor packages, and more particularly, for forming features in semiconductor packages by laser ablation. In one embodiment, the laser systems and methods described herein can be utilized to pattern a substrate to be utilized as a package frame for a semiconductor package having one or more interconnections formed therethrough and/or one or more semiconductor dies disposed therein. The laser systems described herein can produce tunable laser beams for forming features in a substrate or other package structure. Specifically, frequency, pulse width, pulse shape, and pulse energy of laser beams are tunable based on desired sizes of patterned features and on the material in which the patterned features are formed. The adjustability of the laser beams enables rapid and accurate formation of features in semiconductor substrates and packages with controlled depth and topography.
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公开(公告)号:US20210346983A1
公开(公告)日:2021-11-11
申请号:US16871302
申请日:2020-05-11
Applicant: Applied Materials, Inc.
Inventor: Kurtis LESCHKIES , Wei-Sheng LEI , Jeffrey L. FRANKLIN , Jean DELMAS , Han-Wen CHEN , Giback PARK , Steven VERHAVERBEKE
IPC: B23K26/0622 , B23K26/382 , B23K26/40 , H01L21/48 , H01L25/00
Abstract: A method of fabricating a frame to enclose one or more semiconductor dies includes forming one or more features including one or more cavities and one or more through-vias in a substrate by a first laser ablation process, filling the one or more through-vias with a dielectric material, and forming a via-in-via in the dielectric material filled in each of the one or more through-vias by a second laser ablation process. The one or more cavities is configured to enclose one or more semiconductor dies therein. In the first laser ablation process, frequency, pulse width, and pulse energy of a first pulsed laser beam to irradiate the substrate are tuned based on a depth of the one or more features. In the second laser ablation process, frequency, pulse width, and pulse energy of a second pulsed laser beam to irradiate the dielectric material are tuned based on a depth of the via-in-via.
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公开(公告)号:US20190057879A1
公开(公告)日:2019-02-21
申请号:US16046119
申请日:2018-07-26
Applicant: Applied Materials, Inc.
Inventor: Jean DELMAS , Steven VERHAVERBEKE , Kurtis LESCHKIES
IPC: H01L21/324 , H01L21/67
Abstract: Embodiments of the disclosure relate to an apparatus and method for annealing semiconductor substrates. In one embodiment, a batch processing chamber is disclosed. The batch processing chamber includes a chamber body enclosing a processing region, a gas panel configured to provide a processing fluid into the processing region, a condenser fluidly connected to the processing region and a temperature-controlled fluid circuit configured to maintain the processing fluid at a temperature above a condensation point of the processing fluid. The processing region is configured to retain a plurality of substrates during processing. The condenser is configured to condense the processing fluid into a liquid phase.
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公开(公告)号:US20170140983A1
公开(公告)日:2017-05-18
申请号:US15347948
申请日:2016-11-10
Applicant: Applied Materials, Inc.
Inventor: Kurtis LESCHKIES , Steven VERHAVERBEKE
IPC: H01L21/768 , C23C16/50 , H01L21/67 , C23C16/52 , C23C16/56 , C23C16/455 , C23C16/48
CPC classification number: H01L21/76879 , C23C16/02 , C23C16/045 , C23C16/45527 , C23C16/45536 , C23C16/45544 , C23C16/482 , C23C16/50 , C23C16/52 , C23C16/56 , H01L21/67075 , H01L21/76802 , H01L21/76883
Abstract: A method of device processing. The method may include providing a cavity in a layer, directing energetic flux to a bottom surface of the cavity, performing an exposure of the cavity to a moisture-containing ambient, and introducing a fill material in the cavity using an atomic layer deposition (ALD) process, wherein the fill material is selectively deposited on the bottom surface of the cavity with respect to a sidewall of the cavity.
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公开(公告)号:US20210288027A1
公开(公告)日:2021-09-16
申请号:US16814785
申请日:2020-03-10
Applicant: Applied Materials, Inc.
Inventor: Kurtis LESCHKIES , Han-Wen CHEN , Steven VERHAVERBEKE , Giback PARK , Kyuil CHO , Jeffrey L. FRANKLIN , Wei-Sheng LEI
IPC: H01L25/065 , H05K1/14 , H01L25/00 , H01L23/495 , H01L23/522
Abstract: The present disclosure generally relates to stacked miniaturized electronic devices and methods of forming the same. More specifically, embodiments described herein relate to semiconductor device spacers and methods of forming the same. The semiconductor device spacers described herein may be utilized to form stacked semiconductor package assemblies, stacked PCB assemblies, and the like.
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公开(公告)号:US20200243345A1
公开(公告)日:2020-07-30
申请号:US16849604
申请日:2020-04-15
Applicant: Applied Materials, Inc.
Inventor: Jean DELMAS , Steven VERHAVERBEKE , Kurtis LESCHKIES
IPC: H01L21/324 , H01L21/67
Abstract: Disclosed herein is an apparatus and method for annealing semiconductor substrates. In one example a temperature-controlled fluid circuit includes a condenser configured to fluidly connect to an internal volume of a processing chamber. The processing chamber has a body, the internal volume is within the body. The condenser is configured to condense a processing fluid into liquid phase. A source conduit includes a first terminal end that couples to a first port on the body of the processing chamber. The source conduit includes a second terminal end. The first terminal end couples to a gas panel. The gas panel is configured to provide a processing fluid into the internal volume of the processing chamber. A gas conduit includes a first end. The first end couples to the condenser and a second end. The second end is configured to couple to a second port on the body of the processing chamber.
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公开(公告)号:US20200234973A1
公开(公告)日:2020-07-23
申请号:US16842605
申请日:2020-04-07
Applicant: Applied Materials, Inc.
Inventor: Jean DELMAS , Steven VERHAVERBEKE , Kurtis LESCHKIES
IPC: H01L21/324 , H01L21/67
Abstract: Disclosed herein is an apparatus and method for annealing semiconductor substrates. In one example the method of annealing substrates in a processing chamber includes loading a plurality of substrates into an internal volume of the processing chamber. The method includes flowing a processing fluid through a gas conduit into the internal volume. The method further includes measuring a temperature of the gas conduit at one or more position utilizing one or more temperature sensors. The processing fluid in the gas conduit and the internal volume are maintained at a temperature above a condensation point of the processing fluid.
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公开(公告)号:US20190057885A1
公开(公告)日:2019-02-21
申请号:US15681317
申请日:2017-08-18
Applicant: Applied Materials, Inc.
Inventor: Jean DELMAS , Steven VERHAVERBEKE , Kurtis LESCHKIES
IPC: H01L21/67 , H01L21/324 , F27B9/36
Abstract: Embodiments of the disclosure relate to an apparatus and method for annealing one or more semiconductor substrates. In one embodiment, a processing chamber is disclosed. The processing chamber includes a chamber body enclosing an internal volume, a substrate support disposed in the internal volume and configured to support a substrate during processing, a gas panel configured to provide a processing fluid into the internal volume, and a temperature-controlled fluid circuit configured to maintain the processing fluid at a temperature above a condensation point of the processing fluid. The temperature-controlled fluid circuit includes a gas conduit fluidly coupled to a port on the chamber body at a first end and to the gas panel at a second end.
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公开(公告)号:US20220020590A1
公开(公告)日:2022-01-20
申请号:US16928252
申请日:2020-07-14
Applicant: Applied Materials, Inc.
Inventor: Wei-Sheng LEI , Kurtis LESCHKIES , Roman GOUK , Steven VERHAVERBEKE , Visweswaren SIVARAMAKRISHNAN
IPC: H01L21/268 , H01L21/768 , H01L21/67 , H01L21/68 , B23K26/00 , B23K26/386
Abstract: In an embodiment is provided a method of forming a blind via in a substrate comprising a mask layer, a conductive layer, and a dielectric layer that includes conveying the substrate to a scanning chamber; determining one or more properties of the blind via, the one or more properties comprising a top diameter, a bottom diameter, a volume, or a taper angle of about 80° or more; focusing a laser beam at the substrate to remove at least a portion of the mask layer; adjusting the laser process parameters based on the one or more properties; and focusing the laser beam, under the adjusted laser process parameters, to remove at least a portion of the dielectric layer within the volume to form the blind via. In some embodiments, the mask layer can be pre-etched. In another embodiment is provided an apparatus for forming a blind via in a substrate.
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公开(公告)号:US20220013375A1
公开(公告)日:2022-01-13
申请号:US17329948
申请日:2021-05-25
Applicant: Applied Materials, Inc.
Inventor: Jean DELMAS , Steven VERHAVERBEKE , Kurtis LESCHKIES
IPC: H01L21/67 , F27B9/36 , H01L21/677 , H01L21/324
Abstract: Embodiments of the disclosure relate to an apparatus and method for annealing one or more semiconductor substrates. In one embodiment, a processing chamber is disclosed. The processing chamber includes a chamber body enclosing an internal volume, a substrate support disposed in the internal volume and configured to support a substrate during processing, a gas panel configured to provide a processing fluid into the internal volume, and a temperature-controlled fluid circuit configured to maintain the processing fluid at a temperature above a condensation point of the processing fluid. The temperature-controlled fluid circuit includes a gas conduit fluidly coupled to a port on the chamber body at a first end and to the gas panel at a second end.
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