公开(公告)号：US20190206691A1

公开(公告)日：2019-07-04

申请号：US15862522

申请日：2018-01-04

Applicant: Applied Materials, Inc.

Inventor： Yujia ZHAI ,  Xiangxin RUI ,  Lai ZHAO ,  Dong-Kil YIM ,  Soo Young CHOI

IPC: H01L21/28 ,  H01L21/02 ,  H01L29/423 ,  H01L49/02 ,  H01L29/51 ,  H01L29/78

CPC classification number: H01L21/28167 ,  H01L21/02148 ,  H01L21/3105 ,  H01L21/76843 ,  H01L28/56 ,  H01L29/42364 ,  H01L29/513 ,  H01L29/517 ,  H01L29/78

Abstract: Embodiments of the present disclosure generally relate to a layer stack including a dielectric layer having a high K value capable of improving semiconductor display device electrical performance. In one embodiment, the layer stack includes a substrate, a channel layer disposed on the substrate, and a gate insulating layer. The gate insulating layer includes an interface layer disposed on the channel layer and a zirconium dioxide layer disposed on the interface layer. The gate insulating layer has a K value ranging from about 20 to about 50. The high k value of the gate insulating layer reduces the subthreshold swing (SS) causing a higher energy barrier which alleviates the short channel effect and leakage in display devices. Additionally, the high k value of the gate insulating layer enables for a faster driving current that improves brightness and performance of the display device.

公开(公告)号：US20180347037A1

公开(公告)日：2018-12-06

申请号：US15700671

申请日：2017-09-11

Applicant: Applied Materials, Inc.

Inventor： Yujia ZHAI ,  Lai ZHAO ,  Xiangxin RUI ,  Dong Kil YIM ,  Tae Kyung WON ,  Soo Young CHOI

IPC: C23C16/44 ,  H01J37/32

Abstract: Implementations described herein generally relate to methods and apparatus for in-situ removal of unwanted deposition buildup from one or more interior surfaces of a substrate-processing chamber. In one implementation, a method for cleaning a processing chamber is provided. The method comprises introducing a reactive species into a processing chamber having a residual high-k dielectric material formed on one or more interior surfaces of the processing chamber. The reactive species is formed from a halogen-containing gas mixture and the one or more interior surfaces include at least one surface having a coating material formed thereon. The method further comprises reacting the residual high-k dielectric material with the reactive species to form a volatile product. The method further comprises removing the volatile product from the processing chamber. The removal rate of the residual high-k dielectric material is greater than a removal rate of the coating material.

公开(公告)号：US20180026054A1

公开(公告)日：2018-01-25

申请号：US15648167

申请日：2017-07-12

Applicant: Applied Materials, Inc.

Inventor： Xiangxin RUI ,  Lai ZHAO ,  Jrjyan Jerry CHEN ,  Soo Young CHOI ,  Yujia ZHAI

IPC: H01L27/12

CPC classification number: H01L27/1255 ,  H01L27/1222 ,  H01L27/1237 ,  H01L27/1248 ,  H01L27/1259 ,  H01L27/1262 ,  H01L28/55 ,  H01L29/4908 ,  H01L29/78675

Abstract: Embodiments of the disclosure generally provide methods of forming a hybrid film stack that may be used as a capacitor layer or a gate insulating layer with a high dielectric constant as well as film qualities for display applications. In one embodiment, a thin film transistor structure include gate, source and drain electrodes formed on a substrate, and an insulating layer formed on a substrate, wherein the insulating layer is a hybrid film stack having a dielectric layer comprising a zirconium containing material disposed on an interface layer formed above or below the gate, source and drain electrodes.

公开(公告)号：US20230369354A1

公开(公告)日：2023-11-16

申请号：US18221285

申请日：2023-07-12

Applicant: Applied Materials, Inc.

Inventor： Xiangxin RUI ,  Lai ZHAO ,  Jrjyan Jerry CHEN ,  Soo Young CHOI ,  Yujia ZHAI

IPC: H01L27/12 ,  H01L29/49 ,  H01L29/786

CPC classification number: H01L27/1255 ,  H01L27/1248 ,  H01L27/1222 ,  H01L27/1259 ,  H01L28/55 ,  H01L29/4908 ,  H01L29/78675 ,  H01L27/1237 ,  H01L27/1262

Abstract: Embodiments of the disclosure generally provide methods of forming a hybrid film stack that may be used as a capacitor layer or a gate insulating layer with a high dielectric constant as well as film qualities for display applications. In one embodiment, a thin film transistor structure include gate, source and drain electrodes formed on a substrate, and an insulating layer formed on a substrate, wherein the insulating layer is a hybrid film stack having a dielectric layer comprising a zirconium containing material disposed on an interface layer formed above or below the gate, source and drain electrodes.

公开(公告)号：US20210202234A1

公开(公告)日：2021-07-01

申请号：US17182555

申请日：2021-02-23

Applicant: Applied Materials, Inc.

Inventor： Chien-Teh KAO ,  Xiangxin RUI

IPC: H01L21/02 ,  C23C16/455 ,  C23C16/44

Abstract: Embodiments described herein provide a gas supply system for reducing purge time and increasing processing throughput, and an atomic layer deposition (ALD) chamber having the same. The gas supply system includes an inert gas line and a precursor supply line. The inert gas line is configured to be coupled to an inlet of the chamber separate from the precursor supply line. Therefore, the inert gas is supplied concurrently to the precursor supply line and the processing region of the chamber such that total purge time is reduced. The reduction of the total purge time due to the gas supply system increases purge efficiency and increases processing throughput. Furthermore, the gas supply system allows inert gas to be utilized as a dilution gas during flow of precursors.

公开(公告)号：US20190148416A1

公开(公告)日：2019-05-16

申请号：US15889047

申请日：2018-02-05

Applicant: Applied Materials, Inc.

Inventor： Xiangxin RUI ,  Soo Young CHOI ,  Shinichi KURITA ,  Yujia ZHAI ,  Lai ZHAO

IPC: H01L27/12 ,  H01L49/02 ,  H01L29/49 ,  H01L29/786 ,  H01L21/02 ,  H01J37/32 ,  C23C16/40 ,  C23C16/50 ,  C23C16/455 ,  C23C16/52 ,  C23C16/56

Abstract: Embodiments of the present disclosure generally relate to a layer stack including a high K dielectric layer formed over a first dielectric layer and a metal electrode. The high K dielectric layer has a K value of 20 or higher and may be formed as a part of a capacitor, a gate insulating layer, or any suitable insulating layer in electronic devices, such as display devices. The layer stack includes a second dielectric layer disposed on the first dielectric layer and the metal layer, and the high K dielectric layer disposed on the second dielectric layer. The second dielectric layer provides a homogenous surface on which the high K dielectric layer is formed. The homogeneous surface enables the high K dielectric material to be deposited uniformly thereover, resulting in a uniform thickness profile.

公开(公告)号：US20170229554A1

公开(公告)日：2017-08-10

申请号：US15198955

申请日：2016-06-30

Applicant: Applied Materials, Inc.

Inventor： Soo Young CHOI ,  Jrjyan Jerry CHEN ,  Dong-Kil YIM ,  Xiangxin RUI

IPC: H01L29/49 ,  H01L49/02 ,  H01L27/12 ,  H01L21/02

CPC classification number: H01L29/4908 ,  G02F1/136213 ,  G02F1/1368 ,  H01L21/02148 ,  H01L21/02159 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02183 ,  H01L21/02186 ,  H01L21/02189 ,  H01L21/02192 ,  H01L21/02194 ,  H01L21/02274 ,  H01L21/0228 ,  H01L27/1222 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/1255 ,  H01L27/1259 ,  H01L27/3258 ,  H01L27/3262 ,  H01L27/3265 ,  H01L28/40 ,  H01L28/60 ,  H01L2227/323

Abstract: Embodiments of the disclosure generally provide methods of forming a capacitor layer or a gate insulating layer with high dielectric constant as well as film qualities for display applications. In one embodiment, a thin film transistor structure includes source and drain electrodes formed on a substrate, a gate insulating layer formed on a substrate covering the source and drain electrodes, wherein the gate insulating layer is a high-k material having a dielectric constant greater than 10, and a gate electrode formed above or below the gate insulating layer.

公开(公告)号：US20240120349A1

公开(公告)日：2024-04-11

申请号：US18545810

申请日：2023-12-19

Applicant: Applied Materials, Inc.

Inventor： Xiangxin RUI ,  Lai ZHAO ,  Jrjyan Jerry CHEN ,  Soo Young CHOI ,  Yujia ZHAI

IPC: H01L27/12 ,  H01L29/24 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L27/1248 ,  H01L27/1225 ,  H01L27/1262 ,  H01L29/247 ,  H01L29/66969 ,  H01L29/78693

Abstract: Embodiments of the disclosure generally provide methods of forming a capacitor layer or a gate insulating layer with high dielectric constant as well as low film current leakage and desired film qualities for display applications. In one embodiment, a thin film transistor structure includes a dielectric layer formed on a substrate, wherein the dielectric layer is a zirconium containing material comprising aluminum, and gate, source and drain electrodes formed on the substrate, wherein the gate, source and drain electrodes formed above or below the dielectric layer.

公开(公告)号：US20220130873A1

公开(公告)日：2022-04-28

申请号：US17647404

申请日：2022-01-07

Applicant: Applied Materials, Inc.

Inventor： Xiangxin RUI ,  Lai ZHAO ,  Jrjyan Jerry CHEN ,  Soo Young CHOI ,  Yujia ZHAI

IPC: H01L27/12 ,  H01L29/24 ,  H01L29/66 ,  H01L29/786

Abstract: Embodiments of the disclosure generally provide methods of forming a capacitor layer or a gate insulating layer with high dielectric constant as well as low film current leakage and desired film qualities for display applications. In one embodiment, a thin film transistor structure includes a dielectric layer formed on a substrate, wherein the dielectric layer is a zirconium containing material comprising aluminum, and gate, source and drain electrodes formed on the substrate, wherein the gate, source and drain electrodes formed above or below the dielectric layer.

公开(公告)号：US20200083052A1

公开(公告)日：2020-03-12

申请号：US16685074

申请日：2019-11-15

Applicant: Applied Materials, Inc.

Inventor： Yujia ZHAI ,  Xiangxin RUI ,  Lai ZHAO ,  Dong-Kil YIM ,  Soo Young CHOI

IPC: H01L21/28 ,  H01L21/02 ,  H01L29/423 ,  H01L49/02 ,  H01L29/78 ,  H01L29/51

Abstract: Embodiments of the disclosure generally relate to a layer stack containing a dielectric layer having a high K value capable of improving semiconductor display device electrical performance. The layer stack includes a channel layer containing an amorphous silicon layer disposed on a substrate and a gate insulating layer disposed on the channel layer. The gate insulating layer contains a silicon dioxide layer disposed on the channel layer, a zirconium dioxide layer disposed on the silicon dioxide layer, and an interface layer disposed on the zirconium dioxide layer and containing titanium oxide or aluminum oxide. The zirconium dioxide layer is disposed between the silicon dioxide layer and the interface layer and has a thickness of about 250 Å or greater, the gate insulating layer has a K value of about 20 to about 50, and the silicon dioxide layer is disposed between the channel layer and the zirconium dioxide layer.