公开(公告)号：US20240194152A1

公开(公告)日：2024-06-13

申请号：US18556460

申请日：2021-05-07

Applicant: Applied Materials, Inc.

Inventor： Dong Kil YIM ,  Soo Young CHOI ,  Jung Bae KIM

IPC: G09G3/3266 ,  H01L29/786

CPC classification number: G09G3/3266 ,  H01L29/7869 ,  H01L29/78696 ,  G09G2300/0417 ,  G09G2320/0214

Abstract: Disclosed herein is a device including a driving thin film transistor. The driving thin film transistor includes a metal oxide channel, a source electrode in contact with the driving metal oxide channel, and a top gate electrode disposed above the metal oxide channel and physically connected to the driving source electrode.

公开(公告)号：US20210376032A1

公开(公告)日：2021-12-02

申请号：US17382080

申请日：2021-07-21

Applicant: Applied Materials, Inc.

Inventor： Jung Bae KIM ,  Dong Kil YIM ,  Soo Young CHOI ,  Lai ZHAO

IPC: H01L27/32

Abstract: Disclosed herein is a sub-pixel circuit for a display device. The sub-pixel circuit has a driving TFT and at least one switching TFT. The at least one switching TFT is an oxide TFT. The sub-pixel circuit additionally has at least one storage capacitor wherein the storage capacitor has a capacitance between about 1 fF and about 55 fF.

公开(公告)号：US20230378368A1

公开(公告)日：2023-11-23

申请号：US17664335

申请日：2022-05-20

Applicant: Applied Materials, Inc.

Inventor： Fan DEJIU ,  Yun-chu TSAI ,  Dong Kil YIM

IPC: H01L29/786 ,  H01L29/66 ,  H01L21/324

CPC classification number: H01L29/7869 ,  H01L29/66742 ,  H01L29/78696 ,  H01L21/324

Abstract: A method of forming a TFT is provided including forming a buffer layer over a substrate. A metal oxide channel layer is formed over the buffer layer and the channel layer is annealed. A gate insulator layer is formed over the channel layer and an ILD is deposited over the gate insulator layer to form the TFT. The TFT is annealed for a first annealing condition to form an annealed TFT. The annealed TFT is shorted or includes a first threshold voltage of about 0 volt or less. The annealed TFT is annealed for a second annealing condition to form a regenerated TFT having a second threshold voltage greater than the first threshold voltage, the second annealing condition includes a temperature of about 150° C. to about 275° C.

公开(公告)号：US20230274997A1

公开(公告)日：2023-08-31

申请号：US18195196

申请日：2023-05-09

Applicant: Applied Materials, Inc.

Inventor： Rodney S. LIM ,  Jung Bae KIM ,  Jiarui WANG ,  Yi CUI ,  Dong Kil YIM ,  Soo Young CHOI

IPC: H01L23/31 ,  H01L27/12 ,  H01L21/02 ,  H01L29/786

CPC classification number: H01L23/3192 ,  H01L27/1248 ,  H01L21/02211 ,  H01L21/0217 ,  H01L21/02274 ,  H01L29/786

Abstract: Embodiments of the present disclosure generally relate to nitrogen-rich silicon nitride and methods for depositing the same, and transistors and other devices containing the same. In one or more embodiments, a passivation film stack is provided and includes a silicon oxide layer disposed on a workpiece, a nitrogen-rich silicon nitride layer disposed on the silicon oxide layer, and a hydrogen-rich silicon nitride layer disposed on the nitrogen-rich silicon nitride layer. The hydrogen-rich silicon nitride layer has a greater hydrogen concentration than the nitrogen-rich silicon nitride layer.

公开(公告)号：US20210066153A1

公开(公告)日：2021-03-04

申请号：US16557102

申请日：2019-08-30

Applicant: Applied Materials, Inc.

Inventor： Rodney S. LIM ,  Jung Bae KIM ,  Jiarui WANG ,  Yi CUI ,  Dong Kil YIM ,  Soo Young CHOI

IPC: H01L23/31 ,  H01L27/12 ,  H01L29/786 ,  H01L21/02

Abstract: Embodiments of the present disclosure generally relate to nitrogen-rich silicon nitride and methods for depositing the same, and transistors and other devices containing the same. In one or more embodiments, a passivation film stack contains a silicon oxide layer disposed on a workpiece and a nitrogen-rich silicon nitride layer disposed on the silicon oxide layer. The nitrogen-rich silicon nitride layer has a silicon concentration of about 20 at % to about 35 at %, a nitrogen concentration of about 40 at % to about 75 at %, and a hydrogen concentration of about 10 at % to about 35 at %. In one or more examples, the passivation film stack contains the silicon oxide layer, the nitrogen-rich silicon nitride layer, and a third layer containing any type of silicon nitride, such as nitrogen-rich silicon nitride and/or hydrogen-rich silicon nitride.

公开(公告)号：US20240047291A1

公开(公告)日：2024-02-08

申请号：US17641365

申请日：2019-09-10

Applicant: Applied Materials, Inc.

Inventor： Tae Kyung WON ,  Soo Young CHOI ,  Dong Kil YIM ,  Young Dong LEE ,  Zongkai WU ,  Sanjay D. YADAV

IPC: H01L23/31 ,  H01L23/29 ,  H01L21/56 ,  H01L21/02 ,  H01L33/00 ,  H01L33/56 ,  H01L21/285

CPC classification number: H01L23/3192 ,  H01L23/291 ,  H01L21/56 ,  H01L21/02274 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0214 ,  H01L33/0095 ,  H01L33/56 ,  H01L21/285

Abstract: Embodiments of the present disclosure generally relate to moisture barrier films utilized in an organic light emitting diode device. A moisture barrier film is deposited in a high density plasma chemical vapor deposition chamber at a temperature of less than about 250 degrees Celsius, an inductively coupled plasma power frequency of about 2 MHz to about 13.56 MHz or a microwave power frequency of about 2.45 GHz, and a plasma density of about 1011 cm3 to about 1012 cm3. The moisture barrier film comprises a material selected from the group consisting of silicon oxynitride, silicon nitride, and silicon oxide. The moisture barrier film has a thickness of less than about 3,000 Angstroms, a refractive index between about 1.45 and 1.95, and an absorption coefficient of about zero at UV wavelengths. The moisture barrier film may be utilized in a thin film encapsulation structure or a thin film transistor.

公开(公告)号：US20220013670A1

公开(公告)日：2022-01-13

申请号：US17289570

申请日：2020-06-04

Applicant: Applied Materials, Inc.

Inventor： Jung Bae KIM ,  Dong Kil YIM ,  Soo Young CHOI

IPC: H01L29/786

Abstract: Embodiments herein include thin-film transistors (TFTs) including channel layer stacks with layers having differing mobilities. The TFTs disclosed herein transport higher total current through both the low mobility and the high mobility channel layers due to higher carrier density in high mobility channel layer and/or the high mobility channel layers, which increases the speed of response of the TFTs. The TFTs further include a gate structure disposed over the channel layer stack. The gate structure includes one or more gate electrodes, and thus the TFTs are top-gate (TG), double-gate (DG), or bottom-gate (BG) TFTs. The channel layer stack includes a plurality of layers with differing mobilities. The layers with differing mobilities confer various benefits to the TFT. The high mobility layer increases the speed of response of the TFT.

公开(公告)号：US20210225710A1

公开(公告)日：2021-07-22

申请号：US16822755

申请日：2020-03-18

Applicant: APPLIED MATERIALS, INC.

Inventor： Dong Kil YIM ,  Jose-Ignacio Del-Agua Borniquel

IPC: H01L21/8254 ,  H01L29/22 ,  H01L29/66 ,  H01L29/786

Abstract: In some embodiments, a method of processing a substrate disposed atop a substrate support in a physical vapor deposition process chamber includes: (a) forming a plasma from a process gas within a processing region of the physical vapor deposition chamber, wherein the process gas comprises an inert gas to sputter silicon from a surface of a target within the processing region of the physical vapor deposition chamber; and (b) depositing an amorphous silicon layer atop a first layer on the substrate, wherein the first layer comprises one or more metal oxides of indium (In), gallium (Ga), zinc (Zn), tin (Sn) or combinations thereof.

公开(公告)号：US20180350571A1

公开(公告)日：2018-12-06

申请号：US15613862

申请日：2017-06-05

Applicant: Applied Materials, Inc.

Inventor： Yujia ZHAI ,  Wenqing DAI ,  Lai ZHAO ,  Xiangxin RUI ,  Dong Kil YIM ,  Tae Kyung WON ,  Soo Young CHOI

IPC: H01J37/32 ,  C22F1/18 ,  C23C16/455 ,  C23C16/44

Abstract: Implementations described herein generally relate to methods and apparatus for in-situ removal of unwanted deposition buildup from one or more interior surfaces of a substrate-processing chamber. In one implementation, a method for cleaning a processing chamber is provided. The method comprises introducing a reactive species into a processing chamber having a residual ZrO2 containing film formed on one or more interior surfaces of the processing chamber. The reactive species is formed from BCl3 and the one or more interior surfaces includes at least one exposed Al2O3 surface The method further comprises reacting the residual ZrO2 containing film with the reactive species to form a volatile product. The method further comprises removing the volatile product from the processing chamber, wherein a removal rate of the residual ZrO2 containing film is greater than a removal rate of Al2O3.

公开(公告)号：US20240102152A1

公开(公告)日：2024-03-28

申请号：US17768918

申请日：2020-05-11

Applicant: Yun-Chu TSAI ,  Dong Kil YIM ,  Rodney Shunleong LIM ,  Jürgen GRILLMAYER ,  Jung Bae KIM ,  Marcus BENDER ,  Applied Materials, Inc.

Inventor： Yun-Chu TSAI ,  Dong Kil YIM ,  Rodney Shunleong LIM ,  Jürgen GRILLMAYER ,  Jung Bae KIM ,  Marcus BENDER

IPC: C23C14/34 ,  C23C14/08 ,  C23C14/56 ,  H01L21/02

CPC classification number: C23C14/3485 ,  C23C14/083 ,  C23C14/086 ,  C23C14/3464 ,  C23C14/562 ,  H01L21/02565 ,  H01L21/02631

Abstract: A method (480, 580) of depositing layers of a thin-film transistor on a substrate using a sputter deposition source comprising at least one first pair of electrodes and at least one second pair of electrodes, the method comprising moving (482, 582) the substrate to a first vacuum chamber; depositing (484, 584) a first layer of the layers on the substrate by supplying the at least one first pair of electrodes with bipolar pulsed DC voltage, wherein a first material of the first layer comprises a first metal oxide; moving (486, 586) the substrate from the first vacuum chamber to a second vacuum chamber without a vacuum break; and depositing (488, 588) a second layer of the layers on the first layer by supplying the at least one second pair of electrodes with bipolar pulsed DC voltage, wherein a second material of the second layer comprises a second metal oxide, the second material being different from the first material.