公开(公告)号：US20140190632A1

公开(公告)日：2014-07-10

申请号：US14050224

申请日：2013-10-09

Applicant: Applied Materials, Inc.

Inventor： Ajay KUMAR ,  Madhavi CHANDRACHOOD ,  Scott Alan ANDERSON ,  Peter SATITPUNWAYCHA ,  Wai-Fan YAU

IPC: H01J37/32

CPC classification number: H01J37/32651 ,  G03F1/80 ,  H01J37/32357 ,  H01J37/32422 ,  H01J37/32623 ,  H01J37/32871 ,  H01J2237/0225

Abstract: A method and apparatus for etching photomasks is provided herein. In one embodiment, a method of etching a photomask includes providing a process chamber having a substrate support pedestal adapted to receive a photomask substrate thereon. An ion-radical shield is disposed above the pedestal. A substrate is placed upon the pedestal beneath the ion-radical shield. A process gas is introduced into the process chamber and a plasma is formed from the process gas. The substrate is etched predominantly with radicals that pass through the shield.

Abstract translation: 本文提供了蚀刻光掩模的方法和设备。 在一个实施例中，蚀刻光掩模的方法包括提供具有适于在其上接收光掩模基板的基板支撑基座的处理室。 离子基屏蔽设置在基座上方。 将衬底放置在离子基屏蔽下方的基座上。 工艺气体被引入到处理室中，并且从处理气体形成等离子体。 基底主要用通过屏蔽的自由基进行蚀刻。

公开(公告)号：US20160064197A1

公开(公告)日：2016-03-03

申请号：US14939787

申请日：2015-11-12

Applicant: Applied Materials, Inc.

Inventor： Banqiu WU ,  Ajay KUMAR ,  Kartik RAMASWAMY ,  Omkaram NALAMASU

IPC: H01J37/32

CPC classification number: H01J37/32669 ,  H01J37/32009 ,  H01J37/32422 ,  H01J37/3244 ,  H01L21/0273 ,  H01L21/31144

Abstract: The present disclosure provides methods and an apparatus for controlling and modifying line width roughness (LWR) of a photoresist layer with enhanced electron spinning control. In one embodiment, an apparatus for controlling a line width roughness of a photoresist layer disposed on a substrate includes a processing chamber having a chamber body having a top wall, side wall and a bottom wall defining an interior processing region, a support pedestal disposed in the interior processing region of the processing chamber, and a plasma generator source disposed in the processing chamber operable to provide predominantly an electron beam source to the interior processing region.

Abstract translation: 本公开提供了通过增强的电子纺丝控制来控制和修改光致抗蚀剂层的线宽粗糙度（LWR）的方法和装置。 在一个实施例中，用于控制设置在基板上的光致抗蚀剂层的线宽粗糙度的装置包括处理室，该处理室具有室主体，该室主体具有限定内部处理区域的顶壁，侧壁和底壁， 处理室的内部处理区域和设置在处理室中的等离子体发生器源，其可操作以主要向内部处理区域提供电子束源。

公开(公告)号：US20160035577A1

公开(公告)日：2016-02-04

申请号：US14775651

申请日：2014-03-11

Applicant: APPLIED MATERIALS, INC.

Inventor： Wei-Sheng LEI ,  Mohammad Kamruzzaman CHOWDHURY ,  Todd EGAN ,  Brad EATON ,  Madhava Rao YALAMANCHILI ,  Ajay KUMAR

IPC: H01L21/308 ,  H01L21/3065 ,  H01L21/687 ,  B23K26/402 ,  H01L21/67 ,  H01L21/673 ,  H01L21/82 ,  B23K26/364

CPC classification number: H01L21/3086 ,  B23K26/364 ,  B23K26/40 ,  B23K26/402 ,  B23K2103/172 ,  B23K2103/50 ,  B23K2103/56 ,  H01L21/3065 ,  H01L21/30655 ,  H01L21/3081 ,  H01L21/3085 ,  H01L21/67069 ,  H01L21/67196 ,  H01L21/67207 ,  H01L21/67383 ,  H01L21/68707 ,  H01L21/78 ,  H01L21/82

Abstract: Methods of dicing substrates having a plurality of ICs. A method includes forming a multi-layered mask comprising a laser energy absorbing, non-photodefinable topcoat disposed over a water-soluble base layer disposed over the semiconductor substrate. Because the laser light absorbing material layer is non-photodefinable, material costs associated with conventional photo resist formulations may be avoided. The mask is direct-write patterned with a laser scribing process to provide a patterned mask with gaps. The patterning exposes regions of the substrate between the ICs. Absorption of the mask layer within the laser emission band (e.g., UV band and/or green band) promotes good scribe line quality. The substrate may then be plasma etched through the gaps in the patterned mask to singulate the IC with the mask protecting the ICs during the plasma etch. The soluble base layer of the mask may then be dissolved subsequent to singulation, facilitating removal of the layer.

Abstract translation: 具有多个IC的切割基板的方法。 一种方法包括形成多层掩模，该多层掩模包括设置在半导体衬底上的水溶性基底层上的激光能量吸收不可光限定的顶涂层。 因为激光吸收材料层是不可光定型的，所以可以避免与常规光致抗蚀剂配方相关的材料成本。 掩模是用激光划线工艺直接写入图案，以提供具有间隙的图案化掩模。 图案化使IC之间的衬底的区域暴露。 激光发射带（例如，UV带和/或绿色带）内的掩模层的吸收促进了良好的划线质量。 然后可以通过图案化掩模中的间隙等离子体蚀刻衬底，以在等离子体蚀刻期间用掩模保护IC来对IC进行分离。 然后可以在分离后溶解掩模的可溶性基底层，从而有助于去除该层。

公开(公告)号：US20140273490A1

公开(公告)日：2014-09-18

申请号：US14198568

申请日：2014-03-05

Applicant: Applied Materials, Inc.

Inventor： Zhigang MAO ,  Xiaoyi CHEN ,  Amitabh SABHARWAL ,  Ajay KUMAR

IPC: H01L21/033

CPC classification number: H01L21/0338 ,  C23F4/00 ,  G03F1/00 ,  G03F1/24 ,  G03F1/54 ,  G03F1/80 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/3065 ,  H01L21/31122 ,  H01L21/32136 ,  H01L21/32139 ,  H01L21/67069

Abstract: Embodiments of the present invention provides methods to etching a mask layer, e.g., an absorber layer, disposed in a film stack for manufacturing a photomask in EUV applications and phase shift and binary photomask applications. In one embodiment, a method of etching an absorber layer disposed on a photomask includes transferring a film stack into an etching chamber, the film stack having a chromium containing layer partially exposed through a patterned photoresist layer, providing an etching gas mixture including Cl2, O2 and at least one hydrocarbon gas in to a processing chamber, wherein the Cl2 and O2 is supplied at a Cl2:O2 ratio greater than about 9, supplying a RF source power to form a plasma from the etching gas mixture, and etching the chromium containing layer through the patterned photoresist layer in the presence of the plasma.

Abstract translation: 本发明的实施例提供了在EUV应用和相移和二进制光掩模应用中蚀刻设置在膜堆叠中用于制造光掩模的掩模层（例如吸收层）的方法。 在一个实施例中，蚀刻设置在光掩模上的吸收层的方法包括将膜堆叠转移到蚀刻室中，所述膜堆叠具有通过图案化的光致抗蚀剂层部分暴露的含铬层，提供包括Cl 2，O 2的蚀刻气体混合物 和至少一种烃气体输送到处理室中，其中Cl 2和O 2以大于约9的Cl 2：O 2比供应，提供RF源功率以从蚀刻气体混合物形成等离子体，并且蚀刻含铬 在等离子体存在下穿过图案化的光致抗蚀剂层。

公开(公告)号：US20190279902A1

公开(公告)日：2019-09-12

申请号：US15918673

申请日：2018-03-12

Applicant: APPLIED MATERIALS, INC.

Inventor： Jungrae PARK ,  James S. PAPANU ,  Ajay KUMAR ,  Wei-Sheng LEI

IPC: H01L21/78 ,  H01L21/263 ,  H01L21/268 ,  H01L21/3065 ,  H01L21/308 ,  B23K26/00 ,  B23K10/00

Abstract: Methods of dicing semiconductor wafers are described. In an example, a method of dicing a semiconductor wafer having integrated circuits thereon involves forming a mask above the semiconductor wafer, the mask composed of a layer covering and protecting the integrated circuits. The mask is then patterned with a multiple pass laser scribing process to provide a patterned mask with gaps exposing regions of the semiconductor wafer between the integrated circuits, the multiple pass laser scribing process including a first pass along a first edge scribing path, a second pass along a center scribing path, a third pass along a second edge scribing path, a fourth pass along the second edge scribing path, a fifth pass along the center scribing path, and a sixth pass along the first edge scribing path. The semiconductor wafer is then plasma etched through the gaps in the patterned mask to singulate the integrated circuits.

公开(公告)号：US20160181067A1

公开(公告)日：2016-06-23

申请号：US15055032

申请日：2016-02-26

Applicant: Applied Materials, Inc.

Inventor： Saravjeet SINGH ,  Graeme Jamieson SCOTT ,  Ajay KUMAR

IPC: H01J37/32

CPC classification number: H01J37/321 ,  H01J37/32623 ,  H01J37/32633 ,  H01J2237/334

Abstract: Embodiments described herein provide apparatus and methods of etching a substrate using an ion etch chamber having a movable aperture. The ion etch chamber has a chamber body enclosing a processing region, a substrate support disposed in the processing region and having a substrate receiving surface, a plasma source disposed at a wall of the chamber body facing the substrate receiving surface, an ion-radical shield disposed between the plasma source and the substrate receiving surface, and a movable aperture member between the ion-radical shield and the substrate receiving surface. The movable aperture member is actuated by a lift assembly comprising a lift ring and lift supports from the lift ring to the aperture member. The ion-radical shield is supported by shield supports disposed through the aperture member. The aperture size, shape, and/or central axis location may be changed using inserts.

Abstract translation: 本文描述的实施例提供了使用具有可移动孔径的离子蚀刻室蚀刻衬底的设备和方法。 离子蚀刻室具有包围处理区域的室主体，设置在处理区域中并具有基板接收表面的基板支撑件，设置在室主体面向基板接收表面的壁上的等离子体源，离子基屏蔽 设置在等离子体源和基板接收表面之间，以及位于离子基屏蔽和基板接收表面之间的可移动孔径构件。 可移动孔径构件由包括提升环的提升组件和从提升环提升到孔径构件的提升支撑件致动。 离子基屏蔽由通过孔径构件设置的屏蔽支撑件支撑。 孔径尺寸，形状和/或中心轴位置可以使用插入件来改变。

公开(公告)号：US20140255830A1

公开(公告)日：2014-09-11

申请号：US14199575

申请日：2014-03-06

Applicant: Applied Materials, Inc.

Inventor： Banqiu WU ,  Ajay KUMAR

IPC: G03F1/80

CPC classification number: G03F1/80 ,  G03F1/22

Abstract: An apparatus and methods utilized a DC or AC power to supply through a conductive substrate support pedestal to a conductive photomask substrate during a photomask substrate manufacturing process for EUV or other advanced lithography applications are provided. In one embodiment, an apparatus for processing a photomask includes a substrate support pedestal configured to receive a conductive photomask, wherein the conductive photomask is fabricated from a dielectric material substrate with a conductive coating, and at least a conductive path formed in the substrate support pedestal in contact with the photomask substrate configured to be conductive.

Abstract translation: 提供了一种在用于EUV或其它先进光刻应用的光掩模衬底制造过程中利用DC或AC电力通过导电衬底支撑基座提供给导电光掩模衬底的装置和方法。 在一个实施例中，一种用于处理光掩模的设备包括被配置为接收导电光掩模的基板支撑基座，其中导电光掩模由具有导电涂层的介电材料基板制成，并且至少形成在基板支撑基座中的导电路径 与配置为导电的光掩模基板接触。

公开(公告)号：US20250022755A1

公开(公告)日：2025-01-16

申请号：US18898420

申请日：2024-09-26

Applicant: Applied Materials, Inc.

Inventor： Wei-Sheng LEI ,  Brad EATON ,  Madhava Rao YALAMANCHILI ,  Saravjeet SINGH ,  Ajay KUMAR ,  James M. HOLDEN

IPC: H01L21/822 ,  B23K26/36 ,  H01J37/32 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/67 ,  H01L21/683 ,  H01L21/78 ,  H01L23/544

Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer, the mask including a layer covering and protecting the integrated circuits. The mask and a portion of the semiconductor wafer are patterned with a laser scribing process to provide a patterned mask and to form trenches partially into but not through the semiconductor wafer between the integrated circuits. Each of the trenches has a width. The semiconductor wafer is plasma etched through the trenches to form corresponding trench extensions and to singulate the integrated circuits. Each of the corresponding trench extensions has the width.

公开(公告)号：US20190096634A1

公开(公告)日：2019-03-28

申请号：US16203342

申请日：2018-11-28

Applicant: Applied Materials, Inc.

Inventor： Saravjeet SINGH ,  Graeme Jamieson SCOTT ,  Amitabh SABHARWAL ,  Ajay KUMAR

IPC: H01J37/32

Abstract: Embodiments of the present invention generally relate to a method and apparatus for plasma etching substrates and, more specifically, to a method and apparatus with protection for edges, sides and backs of the substrates being processed. Embodiments of the present invention provide an edge protection plate with an aperture smaller in size than a substrate being processed, wherein the edge protection plate may be positioned in close proximity to the substrate in a plasma chamber. The edge protection plate overlaps edges and/or sides on the substrate to provide protection to reflective coatings on the edge, sides, and back of the substrate.

公开(公告)号：US20150064878A1

公开(公告)日：2015-03-05

申请号：US14091014

申请日：2013-11-26

Applicant: APPLIED MATERIALS, INC.

Inventor： Wei-Sheng LEI ,  Brad EATON ,  Aparna IYER ,  Madhava Rao YALAMANCHILI ,  Ajay KUMAR ,  Jungrae PARK

IPC: H01L21/78 ,  B23K26/36 ,  H01L21/67 ,  H01L21/3065 ,  H01L21/308

CPC classification number: H01L21/78 ,  B23K26/0624 ,  B23K26/364 ,  B23K26/40 ,  B23K2103/172 ,  B23K2103/42 ,  B23K2103/50 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/3081 ,  H01L21/67069 ,  H01L21/67207

Abstract: In embodiments, a hybrid wafer or substrate dicing process involving an initial laser scribe and subsequent plasma etch is implemented for die singulation while also removing an oxidation layer from metal bumps on the wafer. In one embodiment, a method includes forming a mask over the semiconductor wafer covering the plurality of ICs, the plurality of ICs including metal bumps or pads with an oxidation layer. The method includes patterning the mask with a laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the ICs. The method includes plasma etching the semiconductor wafer through the gaps in the patterned mask to singulate the plurality of ICs and remove the oxidation layer from the metal bumps or pads.

Abstract translation: 在实施例中，涉及初始激光划片和随后等离子体蚀刻的混合晶片或衬底切割工艺被实现用于裸片分离，同时还从晶片上的金属凸块去除氧化层。 在一个实施例中，一种方法包括在覆盖多个IC的半导体晶片上形成掩模，所述多个IC包括具有氧化层的金属凸块或焊盘。 该方法包括用激光划线工艺对掩模进行图案化以提供具有间隙的图案化掩模，暴露半导体晶片在IC之间的区域。 该方法包括通过图案化掩模中的间隙对半导体晶片进行等离子体蚀刻，以分离多个IC并从金属凸块或焊盘移除氧化层。