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    Dose reduction of patterned metal oxide photoresists
    5.
    发明授权
    Dose reduction of patterned metal oxide photoresists 有权

    公开(公告)号：US11550222B2

    公开(公告)日：2023-01-10

    申请号：US16890867

    申请日：2020-06-02

    Applicant: Applied Materials, Inc.

    Inventor： Tejinder Singh ,  Lifan Yan ,  Abhijit B. Mallick ,  Daniel Lee Diehl ,  Ho-yung Hwang ,  Jothilingam Ramalingam

    IPC: G03F7/09 ,  H01L21/027 ,  H01L21/033 ,  H01L21/308 ,  G03F7/20

    Abstract: Embodiments of the present disclosure generally relate to a multilayer stack used as a mask in extreme ultraviolet (EUV) lithography and methods for forming a multilayer stack. In one embodiment, the method includes forming a carbon layer over a film stack, forming a metal rich oxide layer on the carbon layer by a physical vapor deposition (PVD) process, forming a metal oxide photoresist layer on the metal rich oxide layer, and patterning the metal oxide photoresist layer. The metal oxide photoresist layer is different from the metal rich oxide layer and is formed by a process different from the PVD process. The metal rich oxide layer formed by the PVD process improves adhesion of the metal oxide photoresist layer and increases the secondary electrons during EUV lithography, which leads to decreased EUV dose energies.

    CHEMICAL LINKERS TO IMPART IMPROVED MECHANICAL STRENGTH TO FLOWABLE FILMS
    7.
    发明申请
    CHEMICAL LINKERS TO IMPART IMPROVED MECHANICAL STRENGTH TO FLOWABLE FILMS 审中-公开
    化学连接剂将改进的机械强度提升到流动膜

    公开(公告)号：US20140302690A1

    公开(公告)日：2014-10-09

    申请号：US14019861

    申请日：2013-09-06

    Applicant: Applied Materials, Inc.

    Inventor： Brian S. Underwood ,  Abhijit B. Mallick ,  Nitin K. Ingle

    IPC: H01L21/02

    CPC classification number: H01L21/02126 ,  C23C16/401 ,  C23C16/452 ,  C23C16/45565 ,  C23C16/50 ,  C23C16/56 ,  H01L21/02203 ,  H01L21/02214 ,  H01L21/02274 ,  H01L21/0234 ,  H01L21/02348

    Abstract: Methods forming a low-κ dielectric material on a substrate are described. The methods may include the steps of producing a radical precursor by flowing an unexcited precursor into a remote plasma region, and reacting the radical precursor with a gas-phase silicon precursor to deposit a flowable film on the substrate. The gas-phase silicon precursor may include at least one silicon-and-oxygen containing compound and at least one silicon-and-carbon linker. The flowable film may be cured to form the low-κ dielectric material.

    Abstract translation: 形成低kgr的方法 介绍基板上的介电材料。 该方法可以包括以下步骤：通过将未激发的前体流入远离等离子体区域，并使自由基前体与气相硅前驱物反应以在基底上沉积可流动的膜而产生自由基前体。 气相硅前体可以包括至少一种含硅和氧的化合物和至少一种硅 - 碳连接体。 可流动膜可以固化以形成低温 介电材料。

    Processes for depositing sib films
    8.
    发明授权
    Processes for depositing sib films 有权

    公开(公告)号：US12033848B2

    公开(公告)日：2024-07-09

    申请号：US17352039

    申请日：2021-06-18

    Applicant: Applied Materials, Inc.

    Inventor： Aykut Aydin ,  Rui Cheng ,  Karthik Janakiraman ,  Abhijit B. Mallick ,  Takehito Koshizawa ,  Bo Qi

    IPC: H01L21/02

    CPC classification number: H01L21/02123 ,  H01L21/02211 ,  H01L21/02271

    Abstract: Embodiments of the present disclosure generally relate to processes for forming silicon- and boron-containing films for use in, e.g., spacer-defined patterning applications. In an embodiment, a spacer-defined patterning process is provided. The process includes disposing a substrate in a processing volume of a processing chamber, the substrate having patterned features formed thereon, and flowing a first process gas into the processing volume, the first process gas comprising a silicon-containing species, the silicon-containing species having a higher molecular weight than SiH4. The process further includes flowing a second process gas into the processing volume, the second process gas comprising a boron-containing species, and depositing, under deposition conditions, a conformal film on the patterned features, the conformal film comprising silicon and boron.

    Processes to deposit amorphous-silicon etch protection liner
    9.
    发明授权
    Processes to deposit amorphous-silicon etch protection liner 有权

    公开(公告)号：US12027374B2

    公开(公告)日：2024-07-02

    申请号：US17246209

    申请日：2021-04-30

    Applicant: Applied Materials, Inc.

    Inventor： Zeqing Shen ,  Bo Qi ,  Abhijit B. Mallick

    IPC: H01L21/311 ,  H01L21/02

    CPC classification number: H01L21/31144 ,  H01L21/02211 ,  H01L21/02271 ,  H01L21/31111

    Abstract: Embodiments of the present disclosure generally relate to fabricating electronic devices, such as memory devices. In one or more embodiments, a method for forming a device includes forming a film stack on a substrate, where the film stack contains a plurality of alternating layers of oxide layers and nitride layers and has a stack thickness, and etching the film stack to a first depth to form a plurality of openings between a plurality of structures. The method includes depositing an etch protection liner containing amorphous-silicon on the sidewalls and the bottoms of the structures, removing the etch protection liner from at least the bottoms of the openings, forming a plurality of holes by etching the film stack in the openings to further extend each bottom of the openings to a second depth of the hole, and removing the etch protection liner from the sidewalls.

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