公开(公告)号：US20250096096A1

公开(公告)日：2025-03-20

申请号：US18469243

申请日：2023-09-18

Applicant: Apple Inc.

Inventor： Kumar Nagarajan ,  Flynn P. Carson ,  Karthik Shanmugam ,  Seongmin Lee

IPC: H01L23/498 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L25/16

Abstract: Electronic packages and methods of formation are described. In an embodiment, an electronic package includes one or more electronic components encapsulated in a step molded molding compound layer, and wiring layer spanning a lower step surface, sidewall, and top surface of the step molded molding compound layer. The wiring layer may further extend into a via opening extending through the lower step surface of the molding compound layer.

公开(公告)号：US10991659B2

公开(公告)日：2021-04-27

申请号：US16704671

申请日：2019-12-05

Applicant: Apple Inc.

Inventor： Flynn P. Carson ,  Jun Chung Hsu ,  Meng Chi Lee ,  Shatki S. Chauhan

IPC: H01L23/552 ,  H01L21/78 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/28 ,  H01L23/00

Abstract: Packages including substrate-less integrated components and methods of fabrication are described are described. In an embodiment, a packaging method includes attaching a ground structure to a carrier and a plurality of components face down to the carrier and laterally adjacent to the ground structure. The plurality of components are encapsulated within a molding compound, and the carrier is removed exposing a plurality of component terminals and a plurality of ground structure terminals. A plurality of packages are singulated.

公开(公告)号：US20170025361A1

公开(公告)日：2017-01-26

申请号：US14947353

申请日：2015-11-20

Applicant: Apple Inc.

Inventor： Meng Chi Lee ,  Shakti S. Chauhan ,  Flynn P. Carson ,  Jun Chung Hsu ,  Tha-An Lin

IPC: H01L23/552 ,  H01L21/56

CPC classification number: H01L23/552 ,  H01L21/486 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/49805 ,  H01L23/49816 ,  H01L24/97 ,  H01L2224/16227 ,  H01L2224/97 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/3025 ,  H01L2224/81

Abstract: A system in package (SiP) is disclosed that uses an EMI shield to inhibit EMI or other electrical interference on the components within the SiP. A metal shield may be formed over the SiP. The metal shield may be electrically coupled to a ground layer in a printed circuit board (PCB) to form the EMI shield around the SiP. The substrate of the SiP may include at least some metallization along vertical walls in the end portions of the substrate. The metallization may provide a large contact area for coupling the metal shield to a ground ring coupled to the ground layer in the PCB. The metallization along the vertical walls in the end portions of the substrate may be formed as through-metal vias in a common substrate before singulation to form the SiP.

Abstract translation: 公开了一种封装系统（SiP），其使用EMI屏蔽来抑制SiP内的元件上的EMI或其他电干扰。 可以在SiP上形成金属屏蔽。 金属屏蔽可以电耦合到印刷电路板（PCB）中的接地层，以在SiP周围形成EMI屏蔽。 SiP的衬底可以包括在衬底的端部中沿垂直壁的至少一些金属化。 金属化可以提供用于将金属屏蔽件耦合到耦合到PCB中的接地层的接地环的大的接触面积。 沿着衬底的端部的垂直壁的金属化可以在共形衬底之前形成为通孔金属孔，以形成SiP。

公开(公告)号：US10109593B2

公开(公告)日：2018-10-23

申请号：US14947353

申请日：2015-11-20

Applicant: Apple Inc.

Inventor： Meng Chi Lee ,  Shakti S. Chauhan ,  Flynn P. Carson ,  Jun Chung Hsu ,  Tha-An Lin

IPC: H01L23/552 ,  H01L21/56 ,  H01L23/498 ,  H01L23/00 ,  H01L21/48 ,  H01L23/31

Abstract: A system in package (SiP) is disclosed that uses an EMI shield to inhibit EMI or other electrical interference on the components within the SiP. A metal shield may be formed over the SiP. The metal shield may be electrically coupled to a ground layer in a printed circuit board (PCB) to form the EMI shield around the SiP. The substrate of the SiP may include at least some metallization along vertical walls in the end portions of the substrate. The metallization may provide a large contact area for coupling the metal shield to a ground ring coupled to the ground layer in the PCB. The metallization along the vertical walls in the end portions of the substrate may be formed as through-metal vias in a common substrate before singulation to form the SiP.

公开(公告)号：US20180082858A1

公开(公告)日：2018-03-22

申请号：US15826509

申请日：2017-11-29

Applicant: Apple Inc.

Inventor： Jun Chung Hsu ,  Flynn P. Carson ,  Kwan-Yu Lai

IPC: H01L21/56 ,  H01L21/48 ,  H01L23/00 ,  H01L23/498 ,  H01L23/552 ,  H01L23/31 ,  H05K3/46

CPC classification number: H01L21/568 ,  H01L21/4857 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/5225 ,  H01L23/552 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/131 ,  H01L2224/16235 ,  H01L2224/16245 ,  H01L2224/81005 ,  H01L2224/97 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/3025 ,  H05K3/4682 ,  Y10T29/49156 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/81

Abstract: Method of forming ultra thin coreless substrates are described. In an embodiment, the method utilizes a debond layer including high and low adhesion surface areas to the carrier substrate, and cutting through the low adhesion surface areas to remove a build-up structure from the carrier substrate. An electrical short layer may be formed as a part of or on the debond layer to facilitate electrical testing of the build-up structure prior to debonding, and aid in the formation a “known good” substrate on a support substrate.

公开(公告)号：US09899239B2

公开(公告)日：2018-02-20

申请号：US14935292

申请日：2015-11-06

Applicant: Apple Inc.

Inventor： Jun Chung Hsu ,  Flynn P. Carson ,  Kwan-Yu Lai

IPC: H05K3/02 ,  H05K3/10 ,  H01L21/56 ,  H01L23/498 ,  H01L21/48 ,  H01L23/552 ,  H01L23/31 ,  H01L23/00 ,  H05K3/46

CPC classification number: H01L21/568 ,  H01L21/4857 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/552 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/131 ,  H01L2224/16235 ,  H01L2224/16245 ,  H01L2224/81005 ,  H01L2224/97 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/3025 ,  H05K3/4682 ,  Y10T29/49156 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/81

Abstract: Method of forming ultra thin coreless substrates are described. In an embodiment, the method utilizes a debond layer including high and low adhesion surface areas to the carrier substrate, and cutting through the low adhesion surface areas to remove a build-up structure from the carrier substrate. An electrical short layer may be formed as a part of or on the debond layer to facilitate electrical testing of the build-up structure prior to debonding, and aid in the formation a “known good” substrate on a support substrate.

公开(公告)号：US09721903B2

公开(公告)日：2017-08-01

申请号：US14976199

申请日：2015-12-21

Applicant: Apple Inc.

Inventor： Meng Chi Lee ,  Shakti S. Chauhan ,  Flynn P. Carson ,  Jun Chung Hsu ,  Tha-An Lin

IPC: H01L29/00 ,  H01L23/552 ,  H01L23/528 ,  H01L23/31 ,  H01L23/522 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/552 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/3157 ,  H01L23/5226 ,  H01L23/528 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/97 ,  H01L2924/10253 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/1815 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/3025 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/81

Abstract: A system in package (SiP) is disclosed that uses an EMI shield to inhibit EMI or other electrical interference on the components within the SiP. A metal shield may be formed on an upper surface of an encapsulant encapsulating the SiP. The metal shield may be electrically coupled to a ground layer in a printed circuit board (PCB) to form the EMI shield around the SiP. The metal shield may be electrically coupled to the ground layer using one or more conductive structures located in the encapsulant. The conductive structures may be located on a perimeter of the components in the SiP. The conductive structures may provide a substantially vertical connection between the substrate and the shield on the upper surface of the encapsulant.

公开(公告)号：US20170148744A1

公开(公告)日：2017-05-25

申请号：US15042817

申请日：2016-02-12

Applicant: Apple Inc.

Inventor： Flynn P. Carson ,  Jun Chung Hsu ,  Meng Chi Lee ,  Shakti S. Chauhan

IPC: H01L23/552 ,  H01L23/31 ,  H01L23/498 ,  H01L21/48 ,  H01L21/78 ,  H01L21/56

Abstract: Packages including substrate-less integrated components and methods of fabrication are described are described. In an embodiment, a packaging method includes attaching a ground structure to a carrier and a plurality of components face down to the carrier and laterally adjacent to the ground structure. The plurality of components are encapsulated within a molding compound, and the carrier is removed exposing a plurality of component terminals and a plurality of ground structure terminals. A plurality of packages are singulated.

公开(公告)号：US12074077B2

公开(公告)日：2024-08-27

申请号：US16952567

申请日：2020-11-19

Applicant: Apple Inc.

Inventor： Karthik Shanmugam ,  Flynn P. Carson ,  Jun Zhai ,  Raymundo M. Camenforte ,  Menglu Li

IPC: H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L25/10 ,  H05K1/02 ,  H01L23/48

CPC classification number: H01L23/3121 ,  H01L21/4857 ,  H01L21/568 ,  H01L23/31 ,  H01L23/3157 ,  H01L23/49816 ,  H01L23/4985 ,  H01L23/5385 ,  H01L23/5386 ,  H01L23/5387 ,  H01L24/24 ,  H01L25/0655 ,  H01L25/105 ,  H05K1/0278 ,  H01L23/481 ,  H01L23/5384 ,  H01L2224/24137 ,  H01L2225/06548 ,  H01L2924/18162

Abstract: Flexible packages and electronic devices with integrated flexible packages are described. In an embodiment, a flexibly package includes a first die and a second die encapsulated in a molding compound layer. A compliant redistribution layer (RDL) spans the molding compound layer and both dies, and includes electrical routing formed directly on landing pads of the dies. A notch is formed in the molding compound layer between the dies to facilitate flexure of the compliant RDL.

公开(公告)号：US20220013834A1

公开(公告)日：2022-01-13

申请号：US17484471

申请日：2021-09-24

Applicant: Apple Inc.

Inventor： Angelo V. Marasco ,  Nathan J. Bohney ,  John M. McCambridge ,  Antonio Manenti ,  Laura E. Mayer ,  Scott L. Gooch ,  Jonathan C. Wilson ,  Flynn P. Carson

IPC: H01M50/183 ,  H01M10/42 ,  H01M50/40 ,  H01M50/531 ,  H01M50/543

Abstract: Battery systems according to embodiments of the present technology may include a battery cell having an electrode tab extending from an edge of the battery cell. The systems may also include a module electrically coupled with the battery cell. The module may be characterized by a first surface, a height, and a second surface opposite the first surface. A conductive tab coupled along the first surface of the module may extend from a first end parallel to a plane of the first surface. The conductive tab may be characterized by a curvature proximate a midpoint of the conductive tab. A distal region of the conductive tab may return back across the first surface of the module substantially parallel to the first surface. A distal portion of the electrode tab may be fixedly coupled with the distal region of the conductive tab.