公开(公告)号：US20240106782A1

公开(公告)日：2024-03-28

申请号：US17954748

申请日：2022-09-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Johnathan Robert Alsop ,  Shaizeen Dilawarhusen Aga ,  MOHAMED ASSEM ABD ELMOHSEN IBRAHIM

IPC: H04L51/212 ,  H04L51/234

CPC classification number: H04L51/212 ,  H04L51/234

Abstract: In accordance with described techniques for filtered responses to memory operation messages, a computing system or computing device includes a memory system that receives messages. A filter component in the memory system receives the responses to the memory operation messages, and filters one or more of the responses based on a filterable condition. A tracking logic component tracks the one or more responses as filtered responses for communication completion.

公开(公告)号：US20240069915A1

公开(公告)日：2024-02-29

申请号：US17899231

申请日：2022-08-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Meysam Taassori ,  Shaizeen Dilawarhusen Aga ,  Mohamed Assem Abd ElMohsen Ibrahim ,  Johnathan Robert Alsop

IPC: G06F9/30 ,  G06F12/10 ,  G06F16/22

CPC classification number: G06F9/30036 ,  G06F12/10 ,  G06F16/2237

Abstract: A virtual padding unit provides a virtual padded data structure (e.g., virtually padded matrix) that provides output values for a padded data structure without storing all of the padding elements in memory. When the virtual padding unit receives a virtual memory address of a location in the virtual padded data structure, the virtual padding unit checks whether the location is a non-padded location in the virtual padded data structure or a padded location in the virtual padded data structure. If the location is a padded location in the virtual padded data structure, the virtual padding unit outputs a padding value rather than a value stored in the virtual padded data structure. If the location is a non-padded location in the virtual padded data structure, a value stored at the location is output.

公开(公告)号：US20240004801A1

公开(公告)日：2024-01-04

申请号：US17853340

申请日：2022-06-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Nuwan Jayasena ,  Shaizeen Dilawarhusen Aga ,  Vignesh Adhinarayanan

IPC: G06F12/14 ,  G06F9/30

CPC classification number: G06F12/1408 ,  G06F9/3004 ,  G06F9/30029

Abstract: An encryption circuit includes an iterative block cipher circuit. The iterative block cipher circuit has a counter input for a row index, a key input for receiving a secret key, and an output for providing an encrypted counter value in response to performing a block cipher process using the row index as a counter the secret key. The encryption circuit uses the iterative block cipher circuit during a row operation to a memory.

公开(公告)号：US20240202121A1

公开(公告)日：2024-06-20

申请号：US18068670

申请日：2022-12-20

Applicant: Advanced Micro Devices, Inc.

Inventor： Shaizeen Dilawarhusen Aga ,  Johnathan Robert Alsop ,  Nuwan S Jayasena

IPC: G06F12/0811 ,  G06F12/0891

CPC classification number: G06F12/0811 ,  G06F12/0891

Abstract: Programmable data storage memory hierarchy techniques are described. In one example, a data storage system includes a memory hierarchy and a data movement controller. The memory hierarchy includes a hierarchical arrangement of a plurality of memory buffers. The data movement controller is configured to receive a data movement command and control data movement between the plurality of memory buffers based on the data movement command.

公开(公告)号：US20240201993A1

公开(公告)日：2024-06-20

申请号：US18067506

申请日：2022-12-16

Applicant: Advanced Micro Devices, Inc.

Inventor： Shaizeen Dilawarhusen Aga ,  Leopold Grinberg

IPC: G06F9/30 ,  G06F9/345 ,  G06F9/38

CPC classification number: G06F9/3004 ,  G06F9/345 ,  G06F9/3877

Abstract: Data evaluation using processing-in-memory is described. In accordance with the described techniques, data evaluation logic is loaded into a processing-in-memory component. The processing-in-memory component executes the data evaluation logic to evaluate a minimum number of bits required to retrieve data from, or store data to, at least one memory location. A result is output indicating the number of bits required to represent data at the at least one memory location based on the evaluation.

公开(公告)号：US20240103763A1

公开(公告)日：2024-03-28

申请号：US17953723

申请日：2022-09-27

Applicant: Advanced Micro Devices, Inc.

Inventor： Mahzabeen Islam ,  Shaizeen Dilawarhusen Aga ,  Johnathan Robert Alsop ,  MOHAMED ASSEM ABD ELMOHSEN IBRAHIM ,  Nuwan S Jayasena

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0611 ,  G06F3/0673

Abstract: In accordance with the described techniques for bank-level parallelism for processing in memory, a plurality of commands are received for execution by a processing in memory component embedded in a memory. The memory includes a first bank and a second bank. The plurality of commands include a first stream of commands which cause the processing in memory component to perform operations that access the first bank and a second stream of commands which cause the processing in memory component to perform operations that access the second bank. A next row of the first bank that is to be accessed by the processing in memory component is identified. Further, a precharge command is scheduled to close a first row of the first bank and an activate command is scheduled to open the next row of the first bank in parallel with execution of the second stream of commands.

公开(公告)号：US20240220122A1

公开(公告)日：2024-07-04

申请号：US18147088

申请日：2022-12-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Mohamed Assem Abd ElMohsen Ibrahim ,  Shaizeen Dilawarhusen Aga

IPC: G06F3/06

CPC classification number: G06F3/0613 ,  G06F3/0659 ,  G06F3/0673

Abstract: Partial address memory requests for data are described. In accordance with the described techniques, an accelerator receives a request for data that does not include address information for a data storage location from which the data is to be retrieved. The accelerator identifies at least one data storage location that includes data produced by the accelerator and retrieves the data from the at least one data storage location. A result is then output by the accelerator that includes the data retrieved from the at least one data storage location.

公开(公告)号：US20230401154A1

公开(公告)日：2023-12-14

申请号：US17835810

申请日：2022-06-08

Applicant: Advanced Micro Devices, Inc.

Inventor： Mohamed Assem Abd ElMohsen Ibrahim ,  Onur Kayiran ,  Shaizeen Dilawarhusen Aga ,  Yasuko Eckert

IPC: G06F12/0862

CPC classification number: G06F12/0862 ,  G06F2212/602

Abstract: A system and method for efficiently accessing sparse data for a workload are described. In various implementations, a computing system includes an integrated circuit and a memory for storing tasks of a workload that includes sparse accesses of data items stored in one or more tables. The integrated circuit receives a user query, and generates a result based on multiple data items targeted by the user query. To reduce the latency of processing the workload even with sparse lookup operations performed on the one or more tables, a prefetch engine of the integrated circuit stores a subset of data items in prefetch data storage. The prefetch engine also determines which data items to store in the prefetch data storage based on one or more of a frequency of reuse, a distance or latency of access of a corresponding table of the one more tables, or other.

公开(公告)号：US11681465B2

公开(公告)日：2023-06-20

申请号：US16900526

申请日：2020-06-12

Applicant: Advanced Micro Devices, Inc.

Inventor： Johnathan Alsop ,  Shaizeen Dilawarhusen Aga

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0644 ,  G06F3/0673

Abstract: Systems, apparatuses, and methods for dynamically coalescing multi-bank memory commands to improve command throughput are disclosed. A system includes a processor coupled to a memory via a memory controller. The memory also includes processing-in-memory (PIM) elements which are able to perform computations within the memory. The processor generates memory requests targeting the memory which are sent to the memory controller. The memory controller stores commands received from the processor in a queue, and the memory controller determines whether opportunities exist for coalescing multiple commands together into a single multi-bank command. After coalescing multiple commands into a single combined multi-bank command, the memory controller conveys, across the memory bus to multiple separate banks, the single multi-bank command and a multi-bank code specifying which banks are targeted. The memory banks process the command in parallel, and the PIM elements process the data next to each respective bank.

公开(公告)号：US20240411462A1

公开(公告)日：2024-12-12

申请号：US18207314

申请日：2023-06-08

Applicant: Advanced Micro Devices, Inc.

Inventor： Mohamed Assem Abd ElMohsen Ibrahim ,  Shaizeen Dilawarhusen Aga ,  Mahzabeen Islam

IPC: G06F3/06

Abstract: Local and dynamic triggering of operations executed by a processing-in-memory component is described. In accordance with the described techniques, a processing-in-memory component receives a command from a host for execution by the processing-in-memory component. The processing-in-memory component references a tracking table that includes at least one entry associated with an operation performed as part of executing the command and identifies at least one additional command to be triggered locally after executing the command received from the host. Responsive to identifying that conditions associated with the at least one additional command are satisfied, the processing-in-memory component executes the at least one additional command, independent of instructions from the host.