公开(公告)号：US12131026B2

公开(公告)日：2024-10-29

申请号：US18090916

申请日：2022-12-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Alexandru Dutu ,  Nuwan S Jayasena ,  Niti Madan

IPC: G06F3/06

CPC classification number: G06F3/061 ,  G06F3/0659 ,  G06F3/0673

Abstract: Adaptive scheduling of memory requests and processing-in-memory requests is described. In accordance with the described techniques, a memory controller receives a plurality of processing-in-memory requests and a plurality of non-processing-in-memory requests from a host. The memory controller schedules an order of execution for the plurality of processing-in-memory requests and the plurality of non-processing-in-memory requests based at least in part on a processing-in-memory request stall threshold and a non-processing-in-memory request stall threshold. In response to a system switching (e.g., from executing processing-in-memory requests to executing non-processing-in-memory requests or from executing non-processing-in-memory requests to executing processing-in-memory requests), the memory controller modifies the processing-in-memory request stall threshold and the non-processing-in-memory request stall threshold. The memory controller continues scheduling an order of execution for subsequent requests received from the host using the modified stall thresholds.

公开(公告)号：US20240103745A1

公开(公告)日：2024-03-28

申请号：US17954784

申请日：2022-09-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Niti Madan ,  Johnathan Robert Alsop ,  Alexandru Dutu ,  Mahzabeen Islam ,  Yasuko Eckert ,  Nuwan S Jayasena

IPC: G06F3/06

CPC classification number: G06F3/064 ,  G06F3/0659 ,  G06F3/0604 ,  G06F3/0679

Abstract: A memory controller coupled to a memory module receives both processing-in-memory (PIM) requests and memory requests from a host (e.g., a host processor). The memory controller issues PIM requests to one group of memory banks and concurrently issues memory requests to one or more other groups of memory banks. Accordingly, memory requests are performed on groups of memory banks that would otherwise be idle while PIM requests are performed on the one group of memory banks. Optionally, the memory controller coupled to the memory module also takes various actions when switching between operating in a PIM mode and a non-processing-in-memory mode to reduce or hide overhead when switching between the two modes.

公开(公告)号：US20240220107A1

公开(公告)日：2024-07-04

申请号：US18090916

申请日：2022-12-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Alexandru Dutu ,  Nuwan S Jayasena ,  Niti Madan

IPC: G06F3/06

CPC classification number: G06F3/061 ,  G06F3/0659 ,  G06F3/0673

Abstract: Adaptive scheduling of memory requests and processing-in-memory requests is described. In accordance with the described techniques, a memory controller receives a plurality of processing-in-memory requests and a plurality of non-processing-in-memory requests from a host. The memory controller schedules an order of execution for the plurality of processing-in-memory requests and the plurality of non-processing-in-memory requests based at least in part on a processing-in-memory request stall threshold and a non-processing-in-memory request stall threshold. In response to a system switching (e.g., from executing processing-in-memory requests to executing non-processing-in-memory requests or from executing non-processing-in-memory requests to executing processing-in-memory requests), the memory controller modifies the processing-in-memory request stall threshold and the non-processing-in-memory request stall threshold. The memory controller continues scheduling an order of execution for subsequent requests received from the host using the modified stall thresholds.

公开(公告)号：US12204900B2

公开(公告)日：2025-01-21

申请号：US17953142

申请日：2022-09-26

Applicant: Advanced Micro Devices, Inc.

Inventor： Nuwan S Jayasena

IPC: G06F9/30 ,  G06F15/78

Abstract: Predicates for processing in memory is described. In accordance with the described techniques, a predicate instruction to compute a conditional value based on data stored in a memory is provided to a processing-in-memory component. A response that includes the conditional value computed by the processing-in-memory component is received, and the conditional value is stored in a predicate register. One or more conditional instructions are provided to the processing-in-memory component based on the conditional value stored in the predicate register.

公开(公告)号：US20240202121A1

公开(公告)日：2024-06-20

申请号：US18068670

申请日：2022-12-20

Applicant: Advanced Micro Devices, Inc.

Inventor： Shaizeen Dilawarhusen Aga ,  Johnathan Robert Alsop ,  Nuwan S Jayasena

IPC: G06F12/0811 ,  G06F12/0891

CPC classification number: G06F12/0811 ,  G06F12/0891

Abstract: Programmable data storage memory hierarchy techniques are described. In one example, a data storage system includes a memory hierarchy and a data movement controller. The memory hierarchy includes a hierarchical arrangement of a plurality of memory buffers. The data movement controller is configured to receive a data movement command and control data movement between the plurality of memory buffers based on the data movement command.

公开(公告)号：US20240103763A1

公开(公告)日：2024-03-28

申请号：US17953723

申请日：2022-09-27

Applicant: Advanced Micro Devices, Inc.

Inventor： Mahzabeen Islam ,  Shaizeen Dilawarhusen Aga ,  Johnathan Robert Alsop ,  MOHAMED ASSEM ABD ELMOHSEN IBRAHIM ,  Nuwan S Jayasena

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0611 ,  G06F3/0673

Abstract: In accordance with the described techniques for bank-level parallelism for processing in memory, a plurality of commands are received for execution by a processing in memory component embedded in a memory. The memory includes a first bank and a second bank. The plurality of commands include a first stream of commands which cause the processing in memory component to perform operations that access the first bank and a second stream of commands which cause the processing in memory component to perform operations that access the second bank. A next row of the first bank that is to be accessed by the processing in memory component is identified. Further, a precharge command is scheduled to close a first row of the first bank and an activate command is scheduled to open the next row of the first bank in parallel with execution of the second stream of commands.