公开(公告)号：US20240103745A1

公开(公告)日：2024-03-28

申请号：US17954784

申请日：2022-09-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Niti Madan ,  Johnathan Robert Alsop ,  Alexandru Dutu ,  Mahzabeen Islam ,  Yasuko Eckert ,  Nuwan S Jayasena

IPC: G06F3/06

CPC classification number: G06F3/064 ,  G06F3/0659 ,  G06F3/0604 ,  G06F3/0679

Abstract: A memory controller coupled to a memory module receives both processing-in-memory (PIM) requests and memory requests from a host (e.g., a host processor). The memory controller issues PIM requests to one group of memory banks and concurrently issues memory requests to one or more other groups of memory banks. Accordingly, memory requests are performed on groups of memory banks that would otherwise be idle while PIM requests are performed on the one group of memory banks. Optionally, the memory controller coupled to the memory module also takes various actions when switching between operating in a PIM mode and a non-processing-in-memory mode to reduce or hide overhead when switching between the two modes.

公开(公告)号：US12210780B2

公开(公告)日：2025-01-28

申请号：US17954748

申请日：2022-09-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Johnathan Robert Alsop ,  Shaizeen Dilawarhusen Aga ,  Mohamed Assem Abd Elmohsen Ibrahim

IPC: G06F3/06

Abstract: In accordance with described techniques for filtered responses to memory operation messages, a computing system or computing device includes a memory system that receives messages. A filter component in the memory system receives the responses to the memory operation messages, and filters one or more of the responses based on a filterable condition. A tracking logic component tracks the one or more responses as filtered responses for communication completion.

公开(公告)号：US20240106782A1

公开(公告)日：2024-03-28

申请号：US17954748

申请日：2022-09-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Johnathan Robert Alsop ,  Shaizeen Dilawarhusen Aga ,  MOHAMED ASSEM ABD ELMOHSEN IBRAHIM

IPC: H04L51/212 ,  H04L51/234

CPC classification number: H04L51/212 ,  H04L51/234

Abstract: In accordance with described techniques for filtered responses to memory operation messages, a computing system or computing device includes a memory system that receives messages. A filter component in the memory system receives the responses to the memory operation messages, and filters one or more of the responses based on a filterable condition. A tracking logic component tracks the one or more responses as filtered responses for communication completion.

公开(公告)号：US20240069915A1

公开(公告)日：2024-02-29

申请号：US17899231

申请日：2022-08-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Meysam Taassori ,  Shaizeen Dilawarhusen Aga ,  Mohamed Assem Abd ElMohsen Ibrahim ,  Johnathan Robert Alsop

IPC: G06F9/30 ,  G06F12/10 ,  G06F16/22

CPC classification number: G06F9/30036 ,  G06F12/10 ,  G06F16/2237

Abstract: A virtual padding unit provides a virtual padded data structure (e.g., virtually padded matrix) that provides output values for a padded data structure without storing all of the padding elements in memory. When the virtual padding unit receives a virtual memory address of a location in the virtual padded data structure, the virtual padding unit checks whether the location is a non-padded location in the virtual padded data structure or a padded location in the virtual padded data structure. If the location is a padded location in the virtual padded data structure, the virtual padding unit outputs a padding value rather than a value stored in the virtual padded data structure. If the location is a non-padded location in the virtual padded data structure, a value stored at the location is output.

公开(公告)号：US12118354B2

公开(公告)日：2024-10-15

申请号：US17899231

申请日：2022-08-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Meysam Taassori ,  Shaizeen Dilawarhusen Aga ,  Mohamed Assem Abd ElMohsen Ibrahim ,  Johnathan Robert Alsop

IPC: G06F9/30 ,  G06F12/10 ,  G06F16/22

CPC classification number: G06F9/30036 ,  G06F12/10 ,  G06F16/2237

Abstract: A virtual padding unit provides a virtual padded data structure (e.g., virtually padded matrix) that provides output values for a padded data structure without storing all of the padding elements in memory. When the virtual padding unit receives a virtual memory address of a location in the virtual padded data structure, the virtual padding unit checks whether the location is a non-padded location in the virtual padded data structure or a padded location in the virtual padded data structure. If the location is a padded location in the virtual padded data structure, the virtual padding unit outputs a padding value rather than a value stored in the virtual padded data structure. If the location is a non-padded location in the virtual padded data structure, a value stored at the location is output.

公开(公告)号：US20240103730A1

公开(公告)日：2024-03-28

申请号：US17954671

申请日：2022-09-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Johnathan Robert Alsop ,  Shaizeen Dilawarhusen Aga ,  Mohamed Assem Abd ElMohsen Ibrahim

IPC: G06F3/06

CPC classification number: G06F3/0613 ,  G06F3/0659 ,  G06F3/0673

Abstract: In accordance with described techniques for reduction of parallel memory operation messages, a computing system or computing device includes a memory system that receives memory operation messages. A shared response component in the memory system receives responses to the memory operation messages, and identifies a set of the responses that are coalesceable. The shared response component then coalesces the set of the responses into a combined message for communication completion through a communication path in the memory system.

公开(公告)号：US20250004731A1

公开(公告)日：2025-01-02

申请号：US18214748

申请日：2023-06-27

Applicant: Advanced Micro Devices, Inc.

Inventor： Hashim Sharif ,  Johnathan Robert Alsop

IPC: G06F8/41

Abstract: Cross-component optimizing compiler systems are described. In accordance with the described techniques, machine learning models receive components of source code to be compiled. The machine learning models generate component prediction functions for the components of the source code. A tuning engine selects parameters for the components of the source code based on the component prediction functions. Domain-specific language compilers compile the source code based on the selected parameters.

公开(公告)号：US20240202121A1

公开(公告)日：2024-06-20

申请号：US18068670

申请日：2022-12-20

Applicant: Advanced Micro Devices, Inc.

Inventor： Shaizeen Dilawarhusen Aga ,  Johnathan Robert Alsop ,  Nuwan S Jayasena

IPC: G06F12/0811 ,  G06F12/0891

CPC classification number: G06F12/0811 ,  G06F12/0891

Abstract: Programmable data storage memory hierarchy techniques are described. In one example, a data storage system includes a memory hierarchy and a data movement controller. The memory hierarchy includes a hierarchical arrangement of a plurality of memory buffers. The data movement controller is configured to receive a data movement command and control data movement between the plurality of memory buffers based on the data movement command.

公开(公告)号：US11947487B2

公开(公告)日：2024-04-02

申请号：US17852306

申请日：2022-06-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Johnathan Robert Alsop ,  Karthik Ramu Sangaiah ,  Anthony T. Gutierrez

IPC: G06F15/82

CPC classification number: G06F15/825

Abstract: Methods and systems are disclosed for performing dataflow execution by an accelerated processing unit (APU). Techniques disclosed include decoding information from one or more dataflow instructions. The decoded information is associated with dataflow execution of a computational task. Techniques disclosed further include configuring, based on the decoded information, dataflow circuitry, and, then, executing the dataflow execution of the computational task using the dataflow circuitry.

公开(公告)号：US20240103763A1

公开(公告)日：2024-03-28

申请号：US17953723

申请日：2022-09-27

Applicant: Advanced Micro Devices, Inc.

Inventor： Mahzabeen Islam ,  Shaizeen Dilawarhusen Aga ,  Johnathan Robert Alsop ,  MOHAMED ASSEM ABD ELMOHSEN IBRAHIM ,  Nuwan S Jayasena

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0611 ,  G06F3/0673

Abstract: In accordance with the described techniques for bank-level parallelism for processing in memory, a plurality of commands are received for execution by a processing in memory component embedded in a memory. The memory includes a first bank and a second bank. The plurality of commands include a first stream of commands which cause the processing in memory component to perform operations that access the first bank and a second stream of commands which cause the processing in memory component to perform operations that access the second bank. A next row of the first bank that is to be accessed by the processing in memory component is identified. Further, a precharge command is scheduled to close a first row of the first bank and an activate command is scheduled to open the next row of the first bank in parallel with execution of the second stream of commands.