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    Memory sprinting
    6.
    发明授权
    Memory sprinting 有权

    公开(公告)号：US12197735B2

    公开(公告)日：2025-01-14

    申请号：US18129390

    申请日：2023-03-31

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Vignesh Adhinarayanan ,  Michael Ignatowski ,  Hyung-Dong Lee

    IPC: G06F12/00 ,  G06F3/06

    Abstract: A memory sprint controller, responsive to an indicator of an irregular memory access phase, causes a memory controller to enter a sprint mode in which it temporarily adjusts at least one timing parameter of a dynamic random access memory (DRAM) to reduce a time in which a designated number of activate (ACT) commands are allowed to be dispatched to the DRAM.

    Method And Apparatus For Quantization And Dequantization Of Neural Network Input And Output Data Using Processing-In-Memory
    7.
    发明申请
    Method And Apparatus For Quantization And Dequantization Of Neural Network Input And Output Data Using Processing-In-Memory 有权

    公开(公告)号：US20250006232A1

    公开(公告)日：2025-01-02

    申请号：US18346110

    申请日：2023-06-30

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Ioannis Papadopoulos ,  Vignesh Adhinarayanan ,  Ashwin Aji ,  Jagadish B. Kotra

    IPC: G11C7/10 ,  G06F3/06

    Abstract: An apparatus and method for creating less computationally intensive nodes for a neural network. An integrated circuit includes a host processor and multiple memory channels, each with multiple memory array banks. Each of the memory array banks includes components of a processing-in-memory (PIM) accelerator and a scatter and gather circuit used to dynamically perform quantization operations and dequantization operations that offload these operations from the host processor. The host processor executes a data model that represents a neural network. The memory array banks store a single copy of a particular data value in a single precision. Therefore, the memory array banks avoid storing replications of the same data value with different precisions to be used by a neural network node. The memory array banks dynamically perform quantization operations and dequantization operations on one or more of the weight values, input data values, and activation output values of the neural network.

    MEMORY CONTROLLER AND NEAR-MEMORY SUPPORT FOR SPARSE ACCESSES
    8.
    发明公开
    MEMORY CONTROLLER AND NEAR-MEMORY SUPPORT FOR SPARSE ACCESSES 审中-公开

    公开(公告)号：US20240078017A1

    公开(公告)日：2024-03-07

    申请号：US18226932

    申请日：2023-07-27

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Vignesh Adhinarayanan ,  Niti Madan ,  Marjan Fariborz

    IPC: G06F3/06

    CPC classification number: G06F3/0613 ,  G06F3/0659 ,  G06F3/0673

    Abstract: A data processing system includes a data processor and a memory controller receiving memory access requests from the data processor and generating at least one memory access cycle to a memory system in response to the receiving. The memory controller includes a command queue and a sparse element processor. The command queue is for receiving and storing the memory access requests including a first memory access request including a small element request. The sparse element processor is for causing the memory controller to issue a second memory access request to the memory system in response to the first memory access request with a density greater than a density indicated by the first memory access request.

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