公开(公告)号：US11726837B2

公开(公告)日：2023-08-15

申请号：US17519290

申请日：2021-11-04

Applicant: Advanced Micro Devices, Inc.

Inventor： Karthik Rao ,  Shomit N. Das ,  Xudong An ,  Wei Huang

IPC: G06F9/50 ,  G06F9/48 ,  G06F9/38 ,  H04L67/12 ,  G06F1/3206 ,  G06F13/40 ,  G06F3/06 ,  H04N19/436

CPC classification number: G06F9/5094 ,  G06F9/3867 ,  G06F9/3877 ,  G06F9/4893 ,  G06F9/5011 ,  G06F9/5027 ,  G06F9/5055 ,  H04L67/12 ,  G06F1/3206 ,  G06F3/0613 ,  G06F9/5061 ,  G06F13/409 ,  H04N19/436

Abstract: In some examples, thermal aware optimization logic determines a characteristic (e.g., a workload or type) of a wavefront (e.g., multiple threads). For example, the characteristic indicates whether the wavefront is compute intensive, memory intensive, mixed, and/or another type of wavefront. The thermal aware optimization logic determines temperature information for one or more compute units (CUs) in one or more processing cores. The temperature information includes predictive thermal information indicating expected temperatures corresponding to the one or more CUs and historical thermal information indicating current or past thermal temperatures of at least a portion of a graphics processing unit (GPU). The logic selects the one or more compute units to process the plurality of threads based on the determined characteristic and the temperature information. The logic provides instructions to the selected subset of the plurality of CUs to execute the wavefront.

公开(公告)号：US11544196B2

公开(公告)日：2023-01-03

申请号：US16725971

申请日：2019-12-23

Applicant: Advanced Micro Devices, Inc.

Inventor： SeyedMohammad SeyedzadehDelcheh ,  Shomit N. Das ,  Bradford Michael Beckmann

IPC: G06F12/08 ,  G06F12/0871 ,  G06F12/0897 ,  G06F11/30 ,  G06F12/02

Abstract: Systems, apparatuses, and methods for implementing a multi-tiered approach to cache compression are disclosed. A cache includes a cache controller, light compressor, and heavy compressor. The decision on which compressor to use for compressing cache lines is made based on certain resource availability such as cache capacity or memory bandwidth. This allows the cache to opportunistically use complex algorithms for compression while limiting the adverse effects of high decompression latency on system performance. To address the above issue, the proposed design takes advantage of the heavy compressors for effectively reducing memory bandwidth in high bandwidth memory (HBM) interfaces as long as they do not sacrifice system performance. Accordingly, the cache combines light and heavy compressors with a decision-making unit to achieve reduced off-chip memory traffic without sacrificing system performance.

公开(公告)号：US20210157485A1

公开(公告)日：2021-05-27

申请号：US17029158

申请日：2020-09-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Matthew Tomei ,  Shomit N. Das ,  David A. Wood

IPC: G06F3/06 ,  G06F12/0802

Abstract: Systems, methods, and devices for performing pattern-based cache block compression and decompression. An uncompressed cache block is input to the compressor. Byte values are identified within the uncompressed cache block. A cache block pattern is searched for in a set of cache block patterns based on the byte values. A compressed cache block is output based on the byte values and the cache block pattern. A compressed cache block is input to the decompressor. A cache block pattern is identified based on metadata of the cache block. The cache block pattern is applied to a byte dictionary of the cache block. An uncompressed cache block is output based on the cache block pattern and the byte dictionary. A subset of cache block patterns is determined from a training cache trace based on a set of compressed sizes and a target number of patterns for each size.

公开(公告)号：US20200153757A1

公开(公告)日：2020-05-14

申请号：US16188900

申请日：2018-11-13

Applicant: Advanced Micro Devices, Inc.

Inventor： Srikant Bharadwaj ,  Shomit N. Das

IPC: H04L12/933 ,  H04L12/775

Abstract: A system is described that includes an integrated circuit chip having a network-on-chip. The network-on-chip includes multiple routers arranged in a topology and a separate communication link coupled between each router and each of one or more neighboring routers of that router among the multiple routers in the topology. The integrated circuit chip also includes multiple nodes, each node coupled to a router of the multiple routers. When operating, a given router of the multiple routers keeps a record of operating states of some or all of the multiple routers and corresponding communication links. The given router then routes flits to destination nodes via one or more other routers of the multiple routers based at least in part on the operating states of the some or all of the multiple routers and the corresponding communication links.

公开(公告)号：US10318363B2

公开(公告)日：2019-06-11

申请号：US15338172

申请日：2016-10-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Greg Sadowski ,  Steven E. Raasch ,  Shomit N. Das ,  Wayne Burleson

IPC: G06F11/00 ,  G06F11/30 ,  G06F11/34

Abstract: A system and method for managing operating parameters within a system for optimal power and reliability are described. A device includes a functional unit and a corresponding reliability evaluator. The functional unit provides reliability information to one or more reliability monitors, which translate the information to reliability values. The reliability evaluator determines an overall reliability level for the system based on the reliability values. The reliability monitor compares the actual usage values and the expected usage values. When system has maintained a relatively high level of reliability for a given time interval, the reliability evaluator sends an indication to update operating parameters to reduce reliability of the system, which also reduces power consumption for the system.

公开(公告)号：US12130741B2

公开(公告)日：2024-10-29

申请号：US18058534

申请日：2022-11-23

Applicant: Advanced Micro Devices, Inc.

Inventor： SeyedMohammad SeyedzadehDelcheh ,  Shomit N. Das ,  Bradford Michael Beckmann

IPC: G06F12/02 ,  G06F11/30 ,  G06F12/0871 ,  G06F12/0897

CPC classification number: G06F12/0871 ,  G06F11/3037 ,  G06F12/0246 ,  G06F12/0897 ,  G06F2212/401

Abstract: Systems, apparatuses, and methods for implementing a multi-tiered approach to cache compression are disclosed. A cache includes a cache controller, light compressor, and heavy compressor. The decision on which compressor to use for compressing cache lines is made based on certain resource availability such as cache capacity or memory bandwidth. This allows the cache to opportunistically use complex algorithms for compression while limiting the adverse effects of high decompression latency on system performance. To address the above issue, the proposed design takes advantage of the heavy compressors for effectively reducing memory bandwidth in high bandwidth memory (HBM) interfaces as long as they do not sacrifice system performance. Accordingly, the cache combines light and heavy compressors with a decision-making unit to achieve reduced off-chip memory traffic without sacrificing system performance.

公开(公告)号：US11604738B2

公开(公告)日：2023-03-14

申请号：US16146543

申请日：2018-09-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Shomit N. Das ,  Matthew Tomei ,  David A. Wood

IPC: G06F12/0897 ,  G06F12/0811

Abstract: A processing device is provided which includes memory comprising data cache memory configured to store compressed data and metadata cache memory configured to store metadata, each portion of metadata comprising an encoding used to compress a portion of data. The processing device also includes at least one processor configured to compress portions of data and select, based on one or more utility level metrics, portions of metadata to be stored in the metadata cache memory. The at least one processor is also configured to store, in the metadata cache memory, the portions of metadata selected to be stored in the metadata cache memory, store, in the data cache memory, each portion of compressed data having a selected portion of corresponding metadata stored in the metadata cache memory. Each portion of compressed data, having the selected portion of corresponding metadata stored in the metadata cache memory, is decompressed.

公开(公告)号：US10944422B1

公开(公告)日：2021-03-09

申请号：US16579047

申请日：2019-09-23

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Seyedmohammad Seyedzadehdelcheh ,  Shomit N. Das

IPC: H03M7/30 ,  G06F17/16 ,  G06F40/151

Abstract: Entropy agnostic data encoding includes: receiving, by an encoder, input data including a bit string; generating a plurality of candidate codewords, including encoding the input data bit string with a plurality of binary vectors, wherein the plurality of binary vectors includes a set of deterministic biased binary vectors and a set of random binary vectors; selecting, in dependence upon a predefined criteria, one of the plurality of candidate codewords; and transmitting the selected candidate codeword to a decoder.

公开(公告)号：US10860489B2

公开(公告)日：2020-12-08

申请号：US16176828

申请日：2018-10-31

Applicant: Advanced Micro Devices, Inc.

Inventor： Shomit N. Das ,  Matthew Tomei ,  David A. Wood

IPC: H03M7/00 ,  G06F12/0871 ,  H03M7/30 ,  G06F30/00

Abstract: Techniques are disclosed for designing cache compression algorithms that control how data in caches are compressed. The techniques generate a custom “byte select algorithm” by applying repeated transforms applied to an initial compression algorithm until a set of suitability criteria is met. The suitability criteria include that the “cost” is below a threshold and that a metadata constraint is met. The “cost” is the number of blocks that can be compressed by an algorithm as compared with the “ideal” algorithm. The metadata constraint is the number of bits required for metadata.

公开(公告)号：US10795825B2

公开(公告)日：2020-10-06

申请号：US16232314

申请日：2018-12-26

Applicant: Advanced Micro Devices, Inc.

Inventor： Matthew J. Tomei ,  Philip B. Bedoukian ,  Shomit N. Das

IPC: G06F12/00 ,  G06F12/0897 ,  G06F12/0815

Abstract: An electronic device includes at least one compression-decompression functional block and a hierarchy of cache memories with a first cache memory and a second cache memory. The at least one compression-decompression functional block receives data in an uncompressed state, compresses the data using one of a first compression or a second compression, and, after compressing the data, provides the data to the first cache memory for storage therein. When the data is retrieved from the first cache memory to be stored in the second cache memory, when the data is compressed using the first compression, the compression-decompression functional block decompresses the data to reverse effects of the first compression on the data, thereby restoring the data to the uncompressed state and provides the data compressed using the second compression or in the uncompressed state to the second cache memory for storage therein.