公开(公告)号：US20210157485A1

公开(公告)日：2021-05-27

申请号：US17029158

申请日：2020-09-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Matthew Tomei ,  Shomit N. Das ,  David A. Wood

IPC: G06F3/06 ,  G06F12/0802

Abstract: Systems, methods, and devices for performing pattern-based cache block compression and decompression. An uncompressed cache block is input to the compressor. Byte values are identified within the uncompressed cache block. A cache block pattern is searched for in a set of cache block patterns based on the byte values. A compressed cache block is output based on the byte values and the cache block pattern. A compressed cache block is input to the decompressor. A cache block pattern is identified based on metadata of the cache block. The cache block pattern is applied to a byte dictionary of the cache block. An uncompressed cache block is output based on the cache block pattern and the byte dictionary. A subset of cache block patterns is determined from a training cache trace based on a set of compressed sizes and a target number of patterns for each size.

公开(公告)号：US10884940B2

公开(公告)日：2021-01-05

申请号：US16230618

申请日：2018-12-21

Applicant: Advanced Micro Devices, Inc.

Inventor： John Kalamatianos ,  Shrikanth Ganapathy ,  Shomit Das ,  Matthew Tomei

IPC: G06F12/0893 ,  G06F11/07

Abstract: A method of operating a cache in a computing device includes, in response to receiving a memory access request at the cache, determining compressibility of data specified by the request, selecting in the cache a destination portion for storing the data based on the compressibility of the data and a persistent fault history of the destination portion, and storing a compressed copy of the data in a non-faulted subportion of the destination portion, wherein the persistent fault history indicates that the non-faulted subportion excludes any persistent faults.

公开(公告)号：US12164924B2

公开(公告)日：2024-12-10

申请号：US17033308

申请日：2020-09-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Matthew Tomei ,  Shomit Das

IPC: G06F9/30 ,  G06F12/0875

Abstract: A method includes, in response to receiving an instruction to perform a first operation on first data stored in a memory device, obtaining first compression metadata from the memory device based on an address for the first data, and reducing a number of operations in a set of operations based on the first operation and one or more matching addresses, the one or more matching addresses corresponding to second compression metadata matching the first compression metadata.

公开(公告)号：US10558606B1

公开(公告)日：2020-02-11

申请号：US16118172

申请日：2018-08-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Shomit N. Das ,  Matthew Tomei ,  Shrikanth Ganapathy ,  John Kalamatianos

IPC: G06F13/42 ,  G06F1/3296 ,  H03M13/05

Abstract: Systems, apparatuses, and methods for reliably transmitting data over voltage scaled links are disclosed. A computing system includes at least first and second devices connected via a link. In one implementation, if a data block can be compressed to less than or equal to half the original size of the data block, then the data block is compressed and sent on the link in a single clock cycle rather than two clock cycles. If the data block cannot be compressed to half the original size, but if the data block can be compressed enough to include error correction code (ECC) bits without exceeding the original size, then ECC bits are added to the compressed block which is sent on the link at a reduced voltage. The ECC bits help to correct for any errors that are generated as a result of operating the link at the reduced voltage.

公开(公告)号：US20200133866A1

公开(公告)日：2020-04-30

申请号：US16176828

申请日：2018-10-31

Applicant: Advanced Micro Devices, Inc.

Inventor： Shomit N. Das ,  Matthew Tomei ,  David A. Wood

IPC: G06F12/0871 ,  G06F17/50 ,  H03M7/30

Abstract: The disclosure herein provides techniques for designing cache compression algorithms that control how data in caches are compressed. The techniques generate a custom “byte select algorithm” by applying repeated transforms applied to an initial compression algorithm until a set of suitability criteria is met. The suitability criteria include that the “cost” is below a threshold and that a metadata constraint is met. The “cost” is the number of blocks that can be compressed by an algorithm as compared with the “ideal” algorithm. The metadata constraint is the number of bits required for metadata.

公开(公告)号：US20200073845A1

公开(公告)日：2020-03-05

申请号：US16118172

申请日：2018-08-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Shomit N. Das ,  Matthew Tomei ,  Shrikanth Ganapathy ,  John Kalamatianos

IPC: G06F13/42 ,  H03M13/05 ,  G06F1/32

Abstract: Systems, apparatuses, and methods for reliably transmitting data over voltage scaled links are disclosed. A computing system includes at least first and second devices connected via a link. In one implementation, if a data block can be compressed to less than or equal to half the original size of the data block, then the data block is compressed and sent on the link in a single clock cycle rather than two clock cycles. If the data block cannot be compressed to half the original size, but if the data block can be compressed enough to include error correction code (ECC) bits without exceeding the original size, then ECC bits are added to the compressed block which is sent on the link at a reduced voltage. The ECC bits help to correct for any errors that are generated as a result of operating the link at the reduced voltage.

公开(公告)号：US11604738B2

公开(公告)日：2023-03-14

申请号：US16146543

申请日：2018-09-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Shomit N. Das ,  Matthew Tomei ,  David A. Wood

IPC: G06F12/0897 ,  G06F12/0811

Abstract: A processing device is provided which includes memory comprising data cache memory configured to store compressed data and metadata cache memory configured to store metadata, each portion of metadata comprising an encoding used to compress a portion of data. The processing device also includes at least one processor configured to compress portions of data and select, based on one or more utility level metrics, portions of metadata to be stored in the metadata cache memory. The at least one processor is also configured to store, in the metadata cache memory, the portions of metadata selected to be stored in the metadata cache memory, store, in the data cache memory, each portion of compressed data having a selected portion of corresponding metadata stored in the metadata cache memory. Each portion of compressed data, having the selected portion of corresponding metadata stored in the metadata cache memory, is decompressed.

公开(公告)号：US20220100518A1

公开(公告)日：2022-03-31

申请号：US17033308

申请日：2020-09-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Matthew Tomei ,  Shomit Das

IPC: G06F9/30 ,  G06F12/0875

Abstract: A method includes, in response to receiving an instruction to perform a first operation on first data stored in a memory device, obtaining first compression metadata from the memory device based on an address for the first data, and reducing a number of operations in a set of operations based on the first operation and one or more matching addresses, the one or more matching addresses corresponding to second compression metadata matching the first compression metadata.

公开(公告)号：US10860489B2

公开(公告)日：2020-12-08

申请号：US16176828

申请日：2018-10-31

Applicant: Advanced Micro Devices, Inc.

Inventor： Shomit N. Das ,  Matthew Tomei ,  David A. Wood

IPC: H03M7/00 ,  G06F12/0871 ,  H03M7/30 ,  G06F30/00

Abstract: Techniques are disclosed for designing cache compression algorithms that control how data in caches are compressed. The techniques generate a custom “byte select algorithm” by applying repeated transforms applied to an initial compression algorithm until a set of suitability criteria is met. The suitability criteria include that the “cost” is below a threshold and that a metadata constraint is met. The “cost” is the number of blocks that can be compressed by an algorithm as compared with the “ideal” algorithm. The metadata constraint is the number of bits required for metadata.

公开(公告)号：US12001237B2

公开(公告)日：2024-06-04

申请号：US17029158

申请日：2020-09-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Matthew Tomei ,  Shomit N. Das ,  David A. Wood

IPC: G06F12/00 ,  G06F3/06 ,  G06F12/0802

CPC classification number: G06F3/0608 ,  G06F3/0655 ,  G06F3/0676 ,  G06F3/0679 ,  G06F12/0802

Abstract: Systems, methods, and devices for performing pattern-based cache block compression and decompression. An uncompressed cache block is input to the compressor. Byte values are identified within the uncompressed cache block. A cache block pattern is searched for in a set of cache block patterns based on the byte values. A compressed cache block is output based on the byte values and the cache block pattern. A compressed cache block is input to the decompressor. A cache block pattern is identified based on metadata of the cache block. The cache block pattern is applied to a byte dictionary of the cache block. An uncompressed cache block is output based on the cache block pattern and the byte dictionary. A subset of cache block patterns is determined from a training cache trace based on a set of compressed sizes and a target number of patterns for each size.