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公开(公告)号：US11797665B1
公开(公告)日：2023-10-24
申请号：US16454690
申请日：2019-06-27
发明人： David Kaplan , Marius Evers
CPC分类号： G06F21/53 , G06F9/45558 , G06F21/74 , G06F9/3806 , G06F2009/45587 , G06F2221/033
摘要： A processing system includes a branch prediction structure storing information used to predict the outcome of a branch instruction. The processing system also includes a register storing a first identifier of a first process in response to the processing system changing from a first mode that allows the first process to modify the branch prediction structure to a second mode in which the branch prediction structure is not modifiable. The processing system further includes a processor core that selectively flushes the branch prediction structure based on a comparison of a second identifier of a second process and the first identifier stored in the register. The comparison is performed in response to the second process causing a change from the second mode to the first mode.
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公开(公告)号：US20210173783A1
公开(公告)日：2021-06-10
申请号：US16709831
申请日：2019-12-10
发明人： Aparna Thyagarajan , Ashok Tirupathy Venkatachar , Marius Evers , Angelo Wong , William E. Jones
IPC分类号： G06F12/0862
摘要： Techniques for controlling prefetching of instructions into an instruction cache are provided. The techniques include tracking either or both of branch target buffer misses and instruction cache misses, modifying a throttle toggle based on the tracking, and adjusting prefetch activity based on the throttle toggle.
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公开(公告)号：US10929141B1
公开(公告)日：2021-02-23
申请号：US16293266
申请日：2019-03-05
发明人： David Kaplan , Marius Evers
摘要： A state of a first architectural register in a processing system is changed from a first state to a second state that indicates that the first architectural register is to be monitored during speculative execution. A second architectural register in the processing system is associated with a third state in response to the first architectural register being a source register for a memory load instruction that loads data from a memory into the second architectural register during speculative execution. Use of data in the second architectural register is constrained during speculative operations while the second architectural register is in the third state. In some cases, a “set taint” instruction is executed to change the state of the first architectural register from the first state to the second state.
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公开(公告)号：US20200272463A1
公开(公告)日：2020-08-27
申请号：US16286702
申请日：2019-02-27
IPC分类号： G06F9/30 , G06F12/0875
摘要： A processor and method for handling lock instructions identifies which of a plurality of older store instructions relative to a current lock instruction are able to be locked. The method and processor lock the identified older store instructions as an atomic group with the current lock instruction. The method and processor negatively acknowledge probes until all of the older store instructions in the atomic group have written to cache memory. In some implementations, an atomic grouping unit issues an indication to lock identified older store instructions that are retired and lockable, and in some implementations, also issues an indication to lock older stores that are determined to be lockable that are non-retired.
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5.发明申请公开(公告)号：US20190391813A1
公开(公告)日：2019-12-26
申请号：US16014715
申请日：2018-06-21
发明人： Marius Evers , Dhanaraj Bapurao Tavare , Ashok Tirupathy Venkatachar , Arunachalam Annamalai , Donald A. Priore , Douglas R. Williams
IPC分类号： G06F9/38
摘要： The techniques described herein provide an instruction fetch and decode unit having an operation cache with low latency in switching between fetching decoded operations from the operation cache and fetching and decoding instructions using a decode unit. This low latency is accomplished through a synchronization mechanism that allows work to flow through both the operation cache path and the instruction cache path until that work is stopped due to needing to wait on output from the opposite path. The existence of decoupling buffers in the operation cache path and the instruction cache path allows work to be held until that work is cleared to proceed. Other improvements, such as a specially configured operation cache tag array that allows for detection of multiple hits in a single cycle, also improve latency by, for example, improving the speed at which entries are consumed from a prediction queue that stores predicted address blocks.
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公开(公告)号：US20150026414A1
公开(公告)日：2015-01-22
申请号：US13944148
申请日：2013-07-17
IPC分类号： G06F12/08
摘要： A prefetcher maintains the state of stored prefetch information, such as a prefetch confidence level, when a prefetch would cross a memory page boundary. The maintained prefetch information can be used both to identify whether the stride pattern for a particular sequence of demand requests persists after the memory page boundary has been crossed, and to continue to issue prefetch requests according to the identified pattern. The prefetcher therefore does not have re-identify a stride pattern each time a page boundary is crossed by a sequence of demand requests, thereby improving the efficiency and accuracy of the prefetcher.
摘要翻译： 当预取将跨越内存页边界时，预取器维护存储的预取信息的状态，例如预取置信水平。 可以使用维护的预取信息来识别在存储器页边界已经被越过之后特定的请求请求序列的步幅模式是否持续，并且根据所识别的模式继续发出预取请求。 因此，每次通过一系列请求请求来划分页边界时，预取器不会重新识别步幅，从而提高预取器的效率和准确性。
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公开(公告)号：US20140108740A1
公开(公告)日：2014-04-17
申请号：US13653951
申请日：2012-10-17
发明人： Todd Rafacz , Marius Evers , Chitresh Narasimhaiah
IPC分类号： G06F12/08
CPC分类号： G06F12/0862
摘要： A processing system monitors memory bandwidth available to transfer data from memory to a cache. In addition, the processing system monitors a prefetching accuracy for prefetched data. If the amount of available memory bandwidth is low and the prefetching accuracy is also low, prefetching can be throttled by reducing the amount of data prefetched. The prefetching can be throttled by changing the frequency of prefetching, prefetching depth, prefetching confidence levels, and the like.
摘要翻译： 处理系统监视可用于将数据从存储器传输到高速缓存的存储器带宽。 此外，处理系统监视预取数据的预取精度。 如果可用存储器带宽的数量低，并且预取精度也很低，则可以通过减少预取数据量来限制预取。 可以通过改变预取的频率，预取深度，预取置信水平等来限制预取。
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公开(公告)号：US11704248B2
公开(公告)日：2023-07-18
申请号：US17091993
申请日：2020-11-06
IPC分类号： G06F12/0862 , G06F12/128 , G06F12/1027 , G06F1/3234 , G06F12/0815 , G06F12/1009 , G06F12/0811
CPC分类号： G06F12/0862 , G06F1/3275 , G06F12/0811 , G06F12/0815 , G06F12/1009 , G06F12/1027 , G06F12/128 , G06F2212/602 , G06F2212/65 , G06F2212/68
摘要： A processor core associated with a first cache initiates entry into a powered-down state. In response, information representing a set of entries of the first cache are stored in a retention region that receives a retention voltage while the processor core is in a powered-down state. Information indicating one or more invalidated entries of the set of entries is also stored in the retention region. In response to the processor core initiating exit from the powered-down state, entries of the first cache are restored using the stored information representing the entries and the stored information indicating the at least one invalidated entry.
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公开(公告)号：US10949201B2
公开(公告)日：2021-03-16
申请号：US16286702
申请日：2019-02-27
IPC分类号： G06F9/30 , G06F12/0875 , G06F12/0815
摘要： A processor and method for handling lock instructions identifies which of a plurality of older store instructions relative to a current lock instruction are able to be locked. The method and processor lock the identified older store instructions as an atomic group with the current lock instruction. The method and processor negatively acknowledge probes until all of the older store instructions in the atomic group have written to cache memory. In some implementations, an atomic grouping unit issues an indication to lock identified older store instructions that are retired and lockable, and in some implementations, also issues an indication to lock older stores that are determined to be lockable that are non-retired.
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公开(公告)号：US10915322B2
公开(公告)日：2021-02-09
申请号：US16134440
申请日：2018-09-18
IPC分类号： G06F9/30 , G06F9/38 , G06F1/3296
摘要： A processor predicts a number of loop iterations associated with a set of loop instructions. In response to the predicted number of loop iterations exceeding a first loop iteration threshold, the set of loop instructions are executed in a loop mode that includes placing at least one component of an instruction pipeline of the processor in a low-power mode or state and executing the set of loop instructions from a loop buffer. In response to the predicted number of loop iterations being less than or equal to a second loop iteration threshold, the set of instructions are executed in a non-loop mode that includes maintaining at least one component of the instruction pipeline in a powered up state and executing the set of loop instructions from an instruction fetch unit of the instruction pipeline.
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