公开(公告)号：US20150026414A1

公开(公告)日：2015-01-22

申请号：US13944148

申请日：2013-07-17

Applicant: Advanced Micro Devices, Inc.

Inventor： John Kalamatianos ,  Paul Keltcher ,  Marius Evers ,  Chitresh Narasimhaiah

IPC: G06F12/08

Abstract: A prefetcher maintains the state of stored prefetch information, such as a prefetch confidence level, when a prefetch would cross a memory page boundary. The maintained prefetch information can be used both to identify whether the stride pattern for a particular sequence of demand requests persists after the memory page boundary has been crossed, and to continue to issue prefetch requests according to the identified pattern. The prefetcher therefore does not have re-identify a stride pattern each time a page boundary is crossed by a sequence of demand requests, thereby improving the efficiency and accuracy of the prefetcher.

Abstract translation: 当预取将跨越内存页边界时，预取器维护存储的预取信息的状态，例如预取置信水平。 可以使用维护的预取信息来识别在存储器页边界已经被越过之后特定的请求请求序列的步幅模式是否持续，并且根据所识别的模式继续发出预取请求。 因此，每次通过一系列请求请求来划分页边界时，预取器不会重新识别步幅，从而提高预取器的效率和准确性。

公开(公告)号：US20140181410A1

公开(公告)日：2014-06-26

申请号：US13723093

申请日：2012-12-20

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： John Kalamatianos ,  Edward J. McLellan ,  Paul Keltcher ,  Srilatha Manne ,  Richard E. Klass ,  James M. O'Connor

IPC: G06F12/12

CPC classification number: G06F12/121 ,  G06F12/0802 ,  G06F12/084 ,  G06F12/0864 ,  G06F2212/1028 ,  G06F2212/502 ,  G06F2212/601 ,  Y02D10/13

Abstract: In response to a processor core exiting a low-power state, a cache is set to a minimum size so that fewer than all of the cache's entries are available to store data, thus reducing the cache's power consumption. Over time, the size of the cache can be increased to account for heightened processor activity, thus ensuring that processing efficiency is not significantly impacted by a reduced cache size. In some embodiments, the cache size is increased based on a measured processor performance metric, such as an eviction rate of the cache. In some embodiments, the cache size is increased at regular intervals until a maximum size is reached.

Abstract translation: 响应处理器核心退出低功率状态，将高速缓存设置为最小大小，使得少于所有高速缓存的条目可用于存储数据，从而减少高速缓存的功耗。 随着时间的推移，可以增加高速缓存的大小以考虑到处理器活动的增加，从而确保处理效率不受减小的高速缓存大小的显着影响。 在一些实施例中，基于所测量的处理器性能度量（例如高速缓存的逐出速率）来增加高速缓存大小。 在一些实施例中，高速缓存大小以规则的间隔增加，直到达到最大大小。

公开(公告)号：US10671535B2

公开(公告)日：2020-06-02

申请号：US13944148

申请日：2013-07-17

Applicant: Advanced Micro Devices, Inc.

Inventor： John Kalamatianos ,  Paul Keltcher ,  Marius Evers ,  Chitresh Narasimhaiah

IPC: G06F12/0862 ,  G06F12/06

Abstract: A prefetcher maintains the state of stored prefetch information, such as a prefetch confidence level, when a prefetch would cross a memory page boundary. The maintained prefetch information can be used both to identify whether the stride pattern for a particular sequence of demand requests persists after the memory page boundary has been crossed, and to continue to issue prefetch requests according to the identified pattern. The prefetcher therefore does not have re-identify a stride pattern each time a page boundary is crossed by a sequence of demand requests, thereby improving the efficiency and accuracy of the prefetcher.

公开(公告)号：US09058278B2

公开(公告)日：2015-06-16

申请号：US13720072

申请日：2012-12-19

Applicant: Advanced Micro Devices, Inc.

Inventor： John Kalamatianos ,  Paul Keltcher

IPC: G06F12/08

CPC classification number: G06F12/0862 ,  G06F2212/602 ,  G06F2212/6026

Abstract: A method, an apparatus, and a non-transitory computer readable medium for tracking accuracy and coverage of a prefetcher in a processor are presented. A table is maintained and indexed by an address, wherein each entry in the table corresponds to one address. A number of demand requests that hit in the table on a prefetch, a total number of demand requests, and a number of prefetch requests are counted. The accuracy of the prefetcher is calculated by dividing the number of demand requests that hit in the table on a prefetch by the number of prefetch requests. The coverage of the prefetcher is calculated by dividing the number of demand requests that hit in the table on a prefetch by the total number of demand requests. The table and the counters are reset when a reset condition is reached.

Abstract translation: 提出了一种用于跟踪处理器中的预取器的精度和覆盖率的方法，装置和非暂时计算机可读介质。 表由地址维护和索引，其中表中的每个条目对应于一个地址。 对预取中的表中的一些需求请求，需求请求的总数以及预取请求的数量进行计数。 通过将预取中的表中命中的请求请求数除以预取请求数来计算预取器的准确性。 预取器的覆盖率是通过将预取中的表中命中的请求请求数除以请求请求总数来计算的。 当达到复位条件时，表和计数器被复位。

公开(公告)号：US09058277B2

公开(公告)日：2015-06-16

申请号：US13671801

申请日：2012-11-08

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Sharad Dilip Bade ,  Alok Garg ,  John Kalamatianos ,  Paul Keltcher ,  Marius Evers ,  Chitresh Narasimhaiah

IPC: G06F12/08 ,  G06F9/38

CPC classification number: G06F12/0862 ,  G06F9/3842 ,  G06F11/30 ,  G06F2212/6024 ,  G06F2212/6026 ,  Y02D10/13

Abstract: Methods and systems for prefetching data for a processor are provided. A system is configured for and a method includes selecting one of a first prefetching control logic and a second prefetching control logic of the processor as a candidate feature, capturing the performance metric of the processor over an inactive sample period when the candidate feature is inactive, capturing a performance metric of the processor over an active sample period when the candidate feature is active, comparing the performance metric of the processor for the active and inactive sample periods, and setting a status of the candidate feature as enabled when the performance metric in the active period indicates improvement over the performance metric in the inactive period, and as disabled when the performance metric in the inactive period indicates improvement over the performance metric in the active period.

Abstract translation: 提供了用于为处理器预取数据的方法和系统。 系统被配置用于并且方法包括选择处理器的第一预取控制逻辑和第二预取控制逻辑之一作为候选特征，当候选特征不活动时，在非活动采样周期捕获处理器的性能度量， 当候选特征处于活动状态时，在活动采样周期捕获处理器的性能度量，比较处于活动和非活动采样周期的处理器的性能度量，并且将候选特征的状态设置为使能时的性能度量 活动期间表示在非活动期间的性能指标改善，当非活动期间的性能指标表示改善了活动期间的绩效指标时被禁用。

公开(公告)号：US20140173217A1

公开(公告)日：2014-06-19

申请号：US13720072

申请日：2012-12-19

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： John Kalamatianos ,  Paul Keltcher

IPC: G06F12/08

CPC classification number: G06F12/0862 ,  G06F2212/602 ,  G06F2212/6026

Abstract: A method, an apparatus, and a non-transitory computer readable medium for tracking accuracy and coverage of a prefetcher in a processor are presented. A table is maintained and indexed by an address, wherein each entry in the table corresponds to one address. A number of demand requests that hit in the table on a prefetch, a total number of demand requests, and a number of prefetch requests are counted. The accuracy of the prefetcher is calculated by dividing the number of demand requests that hit in the table on a prefetch by the number of prefetch requests. The coverage of the prefetcher is calculated by dividing the number of demand requests that hit in the table on a prefetch by the total number of demand requests. The table and the counters are reset when a reset condition is reached.

Abstract translation: 提出了一种用于跟踪处理器中的预取器的精度和覆盖率的方法，装置和非暂时计算机可读介质。 表由地址维护和索引，其中表中的每个条目对应于一个地址。 对预取中的表中的一些需求请求，需求请求的总数以及预取请求的数量进行计数。 通过将预取中的表中命中的请求请求数除以预取请求数来计算预取器的准确性。 预取器的覆盖率是通过将预取中的表中命中的请求请求数除以请求请求总数来计算的。 当达到复位条件时，表和计数器被复位。

公开(公告)号：US09021207B2

公开(公告)日：2015-04-28

申请号：US13723093

申请日：2012-12-20

Applicant: Advanced Micro Devices, Inc.

Inventor： John Kalamatianos ,  Edward J. McLellan ,  Paul Keltcher ,  Srilatha Manne ,  Richard E. Klass ,  James M. O'Connor

IPC: G06F12/12

CPC classification number: G06F12/121 ,  G06F12/0802 ,  G06F12/084 ,  G06F12/0864 ,  G06F2212/1028 ,  G06F2212/502 ,  G06F2212/601 ,  Y02D10/13

Abstract: In response to a processor core exiting a low-power state, a cache is set to a minimum size so that fewer than all of the cache's entries are available to store data, thus reducing the cache's power consumption. Over time, the size of the cache can be increased to account for heightened processor activity, thus ensuring that processing efficiency is not significantly impacted by a reduced cache size. In some embodiments, the cache size is increased based on a measured processor performance metric, such as an eviction rate of the cache. In some embodiments, the cache size is increased at regular intervals until a maximum size is reached.

Abstract translation: 响应处理器核心退出低功率状态，将高速缓存设置为最小大小，使得少于所有高速缓存的条目可用于存储数据，从而减少高速缓存的功耗。 随着时间的推移，可以增加高速缓存的大小以考虑到处理器活动的增加，从而确保处理效率不受减小的高速缓存大小的显着影响。 在一些实施例中，基于所测量的处理器性能度量（例如高速缓存的逐出速率）来增加高速缓存大小。 在一些实施例中，高速缓存大小以规则的间隔增加，直到达到最大大小。

公开(公告)号：US20140129780A1

公开(公告)日：2014-05-08

申请号：US13671801

申请日：2012-11-08

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Sharad Dilip Bade ,  Alok Garg ,  John Kalamatianos ,  Paul Keltcher ,  Marius Evers ,  Chitresh Narasimhaiah

IPC: G06F12/08

CPC classification number: G06F12/0862 ,  G06F9/3842 ,  G06F11/30 ,  G06F2212/6024 ,  G06F2212/6026 ,  Y02D10/13

Abstract: Methods and systems for prefetching data for a processor are provided. A system is configured for and a method includes selecting one of a first prefetching control logic and a second prefetching control logic of the processor as a candidate feature, capturing the performance metric of the processor over an inactive sample period when the candidate feature is inactive, capturing a performance metric of the processor over an active sample period when the candidate feature is active, comparing the performance metric of the processor for the active and inactive sample periods, and setting a status of the candidate feature as enabled when the performance metric in the active period indicates improvement over the performance metric in the inactive period, and as disabled when the performance metric in the inactive period indicates improvement over the performance metric in the active period.

Abstract translation: 提供了用于为处理器预取数据的方法和系统。 系统被配置用于并且方法包括选择处理器的第一预取控制逻辑和第二预取控制逻辑之一作为候选特征，当候选特征不活动时，在非活动采样周期捕获处理器的性能度量， 当候选特征处于活动状态时，在活动采样周期捕获处理器的性能度量，比较处于活动和非活动采样周期的处理器的性能度量，并且将候选特征的状态设置为使能时的性能度量 活动期间表示在非活动期间的性能指标改善，当非活动期间的性能指标表示改善了活动期间的绩效指标时被禁用。