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公开(公告)号：US10896044B2
公开(公告)日：2021-01-19
申请号：US16014715
申请日：2018-06-21
发明人： Marius Evers , Dhanaraj Bapurao Tavare , Ashok Tirupathy Venkatachar , Arunachalam Annamalai , Donald A. Priore , Douglas R. Williams
IPC分类号： G06F9/38
摘要： The techniques described herein provide an instruction fetch and decode unit having an operation cache with low latency in switching between fetching decoded operations from the operation cache and fetching and decoding instructions using a decode unit. This low latency is accomplished through a synchronization mechanism that allows work to flow through both the operation cache path and the instruction cache path until that work is stopped due to needing to wait on output from the opposite path. The existence of decoupling buffers in the operation cache path and the instruction cache path allows work to be held until that work is cleared to proceed. Other improvements, such as a specially configured operation cache tag array that allows for detection of multiple hits in a single cycle, also improve latency by, for example, improving the speed at which entries are consumed from a prediction queue that stores predicted address blocks.
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公开(公告)号：US20140340114A1
公开(公告)日：2014-11-20
申请号：US13894014
申请日：2013-05-14
IPC分类号： H03K19/003
CPC分类号： H03K19/003
摘要： An integrated circuit device includes a first signal line for distributing a first signal. The first signal line includes a plurality of branch lines, and a leaf node is defined at an end of each branch line. First logic is coupled to the leaf nodes and operable to generate a first status signal indicative of a collective first logic state of the leaf nodes of the signal line corresponding to the first signal.
摘要翻译： 集成电路装置包括用于分配第一信号的第一信号线。 第一信号线包括多个分支线，并且在每个分支线的末端定义叶节点。 第一逻辑耦合到叶节点并且可操作以产生指示对应于第一信号的信号线的叶节点的集体第一逻辑状态的第一状态信号。
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公开(公告)号：US20220206798A1
公开(公告)日：2022-06-30
申请号：US17698955
申请日：2022-03-18
发明人： Matthew T. Sobel , Donald A. Priore , Alok Garg
摘要： Systems, apparatuses, and methods for implementing scheduler queue assignment logic are disclosed. A processor includes at least a decode unit, scheduler queue assignment logic, scheduler queues, pickers, and execution units. The assignment logic receives a plurality of operations from a decode unit in each clock cycle. The assignment logic includes a separate logical unit for each different type of operation which is executable by the different execution units of the processor. For each different type of operation, the assignment logic determines which of the possible assignment permutations are valid for assigning different numbers of operations to scheduler queues in a given clock cycle. The assignment logic receives an indication of how many operations to assign in the given clock cycle, and then the assignment logic selects one of the valid assignment permutations for the number of operations specified by the indication.
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公开(公告)号：US11294678B2
公开(公告)日：2022-04-05
申请号：US15991088
申请日：2018-05-29
发明人： Matthew T. Sobel , Donald A. Priore , Alok Garg
摘要： Systems, apparatuses, and methods for implementing scheduler queue assignment logic are disclosed. A processor includes at least a decode unit, scheduler queue assignment logic, scheduler queues, pickers, and execution units. The assignment logic receives a plurality of operations from a decode unit in each clock cycle. The assignment logic includes a separate logical unit for each different type of operation which is executable by the different execution units of the processor. For each different type of operation, the assignment logic determines which of the possible assignment permutations are valid for assigning different numbers of operations to scheduler queues in a given clock cycle. The assignment logic receives an indication of how many operations to assign in the given clock cycle, and then the assignment logic selects one of the valid assignment permutations for the number of operations specified by the indication.
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5.发明申请公开(公告)号：US20190391813A1
公开(公告)日：2019-12-26
申请号：US16014715
申请日：2018-06-21
发明人： Marius Evers , Dhanaraj Bapurao Tavare , Ashok Tirupathy Venkatachar , Arunachalam Annamalai , Donald A. Priore , Douglas R. Williams
IPC分类号： G06F9/38
摘要： The techniques described herein provide an instruction fetch and decode unit having an operation cache with low latency in switching between fetching decoded operations from the operation cache and fetching and decoding instructions using a decode unit. This low latency is accomplished through a synchronization mechanism that allows work to flow through both the operation cache path and the instruction cache path until that work is stopped due to needing to wait on output from the opposite path. The existence of decoupling buffers in the operation cache path and the instruction cache path allows work to be held until that work is cleared to proceed. Other improvements, such as a specially configured operation cache tag array that allows for detection of multiple hits in a single cycle, also improve latency by, for example, improving the speed at which entries are consumed from a prediction queue that stores predicted address blocks.
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公开(公告)号：US09300293B2
公开(公告)日：2016-03-29
申请号：US13894014
申请日：2013-05-14
IPC分类号： H03K19/00 , G05F1/10 , G05F3/02 , H03K19/003
CPC分类号： H03K19/003
摘要： An integrated circuit device includes a first signal line for distributing a first signal. The first signal line includes a plurality of branch lines, and a leaf node is defined at an end of each branch line. First logic is coupled to the leaf nodes and operable to generate a first status signal indicative of a collective first logic state of the leaf nodes of the signal line corresponding to the first signal.
摘要翻译： 集成电路装置包括用于分配第一信号的第一信号线。 第一信号线包括多个分支线，并且在每个分支线的末端定义叶节点。 第一逻辑耦合到叶节点并且可操作以产生指示对应于第一信号的信号线的叶节点的集体第一逻辑状态的第一状态信号。
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