Invention Application
- Patent Title: PROCESSOR WITH ACCELERATED LOCK INSTRUCTION OPERATION
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Application No.: US16286702Application Date: 2019-02-27
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Publication No.: US20200272463A1Publication Date: 2020-08-27
- Inventor: Scott Thomas Bingham , Marius Evers , Krishnan V. Ramani , Thomas Kunjan
- Applicant: Advanced Micro Devices, Inc.
- Main IPC: G06F9/30
- IPC: G06F9/30 ; G06F12/0875

Abstract:
A processor and method for handling lock instructions identifies which of a plurality of older store instructions relative to a current lock instruction are able to be locked. The method and processor lock the identified older store instructions as an atomic group with the current lock instruction. The method and processor negatively acknowledge probes until all of the older store instructions in the atomic group have written to cache memory. In some implementations, an atomic grouping unit issues an indication to lock identified older store instructions that are retired and lockable, and in some implementations, also issues an indication to lock older stores that are determined to be lockable that are non-retired.
Public/Granted literature
- US10949201B2 Processor with accelerated lock instruction operation Public/Granted day:2021-03-16
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