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    Speculative execution using a page-level tracked load order queue
    1.
    发明授权
    Speculative execution using a page-level tracked load order queue 有权

    公开(公告)号：US11194583B2

    公开(公告)日：2021-12-07

    申请号：US16658688

    申请日：2019-10-21

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Krishnan V. Ramani

    IPC: G06F9/38 ,  G06F9/30

    Abstract: Speculative execution using a page-level tracked load order queue includes: determining that a first load instruction targets a determined memory region; and in response to the first load instruction targeting the determined memory region, adding an entry to a page-level tracked load order queue instead of a load order queue, where the entry indicates a page address of a target of the first load instruction.

    SPECULATIVE INSTRUCTION WAKEUP TO TOLERATE DRAINING DELAY OF MEMORY ORDERING VIOLATION CHECK BUFFERS
    2.
    发明申请
    SPECULATIVE INSTRUCTION WAKEUP TO TOLERATE DRAINING DELAY OF MEMORY ORDERING VIOLATION CHECK BUFFERS 审中-公开

    公开(公告)号：US20200319889A1

    公开(公告)日：2020-10-08

    申请号：US16671097

    申请日：2019-10-31

    Applicant: Advanced Micro Devices, Inc.

    Inventor： John Kalamatianos ,  Susumu Mashimo ,  Krishnan V. Ramani ,  Scott Thomas Bingham

    IPC: G06F9/38 ,  G06F9/30

    Abstract: A technique for speculatively executing load-dependent instructions includes detecting that a memory ordering consistency queue is full for a completed load instruction. The technique also includes storing data loaded by the completed load instruction into a storage location for storing data when the memory ordering consistency queue is full. The technique further includes speculatively executing instructions that are dependent on the completed load instruction. The technique also includes in response to a slot becoming available in the memory ordering consistency queue, replaying the load instruction. The technique further includes in response to receiving loaded data for the replayed load instruction, testing for a data mis-speculation by comparing the loaded data for the replayed load instruction with the data loaded by the completed load instruction that is stored in the storage location.

    Processor with accelerated lock instruction operation
    3.
    发明授权
    Processor with accelerated lock instruction operation 有权

    公开(公告)号：US10949201B2

    公开(公告)日：2021-03-16

    申请号：US16286702

    申请日：2019-02-27

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Scott Thomas Bingham ,  Marius Evers ,  Krishnan V. Ramani ,  Thomas Kunjan

    IPC: G06F9/30 ,  G06F12/0875 ,  G06F12/0815

    Abstract: A processor and method for handling lock instructions identifies which of a plurality of older store instructions relative to a current lock instruction are able to be locked. The method and processor lock the identified older store instructions as an atomic group with the current lock instruction. The method and processor negatively acknowledge probes until all of the older store instructions in the atomic group have written to cache memory. In some implementations, an atomic grouping unit issues an indication to lock identified older store instructions that are retired and lockable, and in some implementations, also issues an indication to lock older stores that are determined to be lockable that are non-retired.

    Apparatus and method for resynchronization prediction with variable upgrade and downgrade capability
    5.
    发明授权
    Apparatus and method for resynchronization prediction with variable upgrade and downgrade capability 有权

    公开(公告)号：US11099846B2

    公开(公告)日：2021-08-24

    申请号：US16013069

    申请日：2018-06-20

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Krishnan V. Ramani ,  Chetana N. Keltcher

    IPC: G06F9/30 ,  G06F9/38

    Abstract: A method and apparatus generates control information that indicates whether to change a counter value associated with a particular load instruction. In response to the control information, the method and apparatus causes a hysteresis effect for operating between a speculative mode and a non-speculative mode based on the counter value. The hysteresis effect is in favor of the non-speculative mode. The method and apparatus causes the hysteresis effect by incrementing the counter value associated with the particular load instruction by a first value or decrementing the counter value by a second value. The first value is greater than the second value.

    PROCESSOR WITH ACCELERATED LOCK INSTRUCTION OPERATION
    6.
    发明申请
    PROCESSOR WITH ACCELERATED LOCK INSTRUCTION OPERATION 审中-公开

    公开(公告)号：US20200272463A1

    公开(公告)日：2020-08-27

    申请号：US16286702

    申请日：2019-02-27

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Scott Thomas Bingham ,  Marius Evers ,  Krishnan V. Ramani ,  Thomas Kunjan

    IPC: G06F9/30 ,  G06F12/0875

    Abstract: A processor and method for handling lock instructions identifies which of a plurality of older store instructions relative to a current lock instruction are able to be locked. The method and processor lock the identified older store instructions as an atomic group with the current lock instruction. The method and processor negatively acknowledge probes until all of the older store instructions in the atomic group have written to cache memory. In some implementations, an atomic grouping unit issues an indication to lock identified older store instructions that are retired and lockable, and in some implementations, also issues an indication to lock older stores that are determined to be lockable that are non-retired.

    Address-based filtering for load/store speculation
    9.
    发明授权
    Address-based filtering for load/store speculation 有权

    公开(公告)号：US11645073B2

    公开(公告)日：2023-05-09

    申请号：US17238844

    申请日：2021-04-23

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： John Kalamatianos ,  Krishnan V. Ramani ,  Susumu Mashimo

    IPC: G06F9/38 ,  G06F9/30 ,  G06F9/35

    CPC classification number: G06F9/30043 ,  G06F9/35 ,  G06F9/3842

    Abstract: Address-based filtering for load/store speculation includes maintaining a filtering table including table entries associated with ranges of addresses; in response to receiving an ordering check triggering transaction, querying the filtering table using a target address of the ordering check triggering transaction to determine if an instruction dependent upon the ordering check triggering transaction has previously been generated a physical address; and in response to determining that the filtering table lacks an indication that the instruction dependent upon the ordering check triggering transaction has previously been generated a physical address, bypassing a lookup operation in an ordering violation memory structure to determine whether the instruction dependent upon the ordering check triggering transaction is currently in-flight.

    Speculative instruction wakeup to tolerate draining delay of memory ordering violation check buffers
    10.
    发明授权
    Speculative instruction wakeup to tolerate draining delay of memory ordering violation check buffers 有权

    公开(公告)号：US11113065B2

    公开(公告)日：2021-09-07

    申请号：US16671097

    申请日：2019-10-31

    Applicant: Advanced Micro Devices, Inc.

    Inventor： John Kalamatianos ,  Susumu Mashimo ,  Krishnan V. Ramani ,  Scott Thomas Bingham

    IPC: G06F9/38 ,  G06F9/30

    Abstract: A technique for speculatively executing load-dependent instructions includes detecting that a memory ordering consistency queue is full for a completed load instruction. The technique also includes storing data loaded by the completed load instruction into a storage location for storing data when the memory ordering consistency queue is full. The technique further includes speculatively executing instructions that are dependent on the completed load instruction. The technique also includes in response to a slot becoming available in the memory ordering consistency queue, replaying the load instruction. The technique further includes in response to receiving loaded data for the replayed load instruction, testing for a data mis-speculation by comparing the loaded data for the replayed load instruction with the data loaded by the completed load instruction that is stored in the storage location.

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