知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

10 records (took 0.018 seconds)

    Control flow guided lock address prefetch and filtering
    2.
    发明授权
    Control flow guided lock address prefetch and filtering 有权

    公开(公告)号：US11243884B2

    公开(公告)日：2022-02-08

    申请号：US16190111

    申请日：2018-11-13

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Susumu Mashimo ,  John Kalamatianos

    IPC: G06F12/0862

    Abstract: A method of prefetching target data includes, in response to detecting a lock-prefixed instruction for execution in a processor, determining a predicted target memory location for the lock-prefixed instruction based on control flow information associating the lock-prefixed instruction with the predicted target memory location. Target data is prefetched from the predicted target memory location to a cache coupled with the processor, and after completion of the prefetching, the lock-prefixed instruction is executed in the processor using the prefetched target data.

    Address-based filtering for load/store speculation
    3.
    发明授权
    Address-based filtering for load/store speculation 有权

    公开(公告)号：US11645073B2

    公开(公告)日：2023-05-09

    申请号：US17238844

    申请日：2021-04-23

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： John Kalamatianos ,  Krishnan V. Ramani ,  Susumu Mashimo

    IPC: G06F9/38 ,  G06F9/30 ,  G06F9/35

    CPC classification number: G06F9/30043 ,  G06F9/35 ,  G06F9/3842

    Abstract: Address-based filtering for load/store speculation includes maintaining a filtering table including table entries associated with ranges of addresses; in response to receiving an ordering check triggering transaction, querying the filtering table using a target address of the ordering check triggering transaction to determine if an instruction dependent upon the ordering check triggering transaction has previously been generated a physical address; and in response to determining that the filtering table lacks an indication that the instruction dependent upon the ordering check triggering transaction has previously been generated a physical address, bypassing a lookup operation in an ordering violation memory structure to determine whether the instruction dependent upon the ordering check triggering transaction is currently in-flight.

    Speculative instruction wakeup to tolerate draining delay of memory ordering violation check buffers
    4.
    发明授权
    Speculative instruction wakeup to tolerate draining delay of memory ordering violation check buffers 有权

    公开(公告)号：US11113065B2

    公开(公告)日：2021-09-07

    申请号：US16671097

    申请日：2019-10-31

    Applicant: Advanced Micro Devices, Inc.

    Inventor： John Kalamatianos ,  Susumu Mashimo ,  Krishnan V. Ramani ,  Scott Thomas Bingham

    IPC: G06F9/38 ,  G06F9/30

    Abstract: A technique for speculatively executing load-dependent instructions includes detecting that a memory ordering consistency queue is full for a completed load instruction. The technique also includes storing data loaded by the completed load instruction into a storage location for storing data when the memory ordering consistency queue is full. The technique further includes speculatively executing instructions that are dependent on the completed load instruction. The technique also includes in response to a slot becoming available in the memory ordering consistency queue, replaying the load instruction. The technique further includes in response to receiving loaded data for the replayed load instruction, testing for a data mis-speculation by comparing the loaded data for the replayed load instruction with the data loaded by the completed load instruction that is stored in the storage location.

    Address-based filtering for load/store speculation
    5.
    发明授权
    Address-based filtering for load/store speculation 有权

    公开(公告)号：US10990393B1

    公开(公告)日：2021-04-27

    申请号：US16658474

    申请日：2019-10-21

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： John Kalamatianos ,  Krishnan V. Ramani ,  Susumu Mashimo

    IPC: G06F9/30 ,  G06F9/38 ,  G06F9/35

    Abstract: Address-based filtering for load/store speculation includes maintaining a filtering table including table entries associated with ranges of addresses; in response to receiving an ordering check triggering transaction, querying the filtering table using a target address of the ordering check triggering transaction to determine if an instruction dependent upon the ordering check triggering transaction has previously been generated a physical address; and in response to determining that the filtering table lacks an indication that the instruction dependent upon the ordering check triggering transaction has previously been generated a physical address, bypassing a lookup operation in an ordering violation memory structure to determine whether the instruction dependent upon the ordering check triggering transaction is currently in-flight.

    SPECULATIVE INSTRUCTION WAKEUP TO TOLERATE DRAINING DELAY OF MEMORY ORDERING VIOLATION CHECK BUFFERS
    9.
    发明申请
    SPECULATIVE INSTRUCTION WAKEUP TO TOLERATE DRAINING DELAY OF MEMORY ORDERING VIOLATION CHECK BUFFERS 审中-公开

    公开(公告)号：US20200319889A1

    公开(公告)日：2020-10-08

    申请号：US16671097

    申请日：2019-10-31

    Applicant: Advanced Micro Devices, Inc.

    Inventor： John Kalamatianos ,  Susumu Mashimo ,  Krishnan V. Ramani ,  Scott Thomas Bingham

    IPC: G06F9/38 ,  G06F9/30

    Abstract: A technique for speculatively executing load-dependent instructions includes detecting that a memory ordering consistency queue is full for a completed load instruction. The technique also includes storing data loaded by the completed load instruction into a storage location for storing data when the memory ordering consistency queue is full. The technique further includes speculatively executing instructions that are dependent on the completed load instruction. The technique also includes in response to a slot becoming available in the memory ordering consistency queue, replaying the load instruction. The technique further includes in response to receiving loaded data for the replayed load instruction, testing for a data mis-speculation by comparing the loaded data for the replayed load instruction with the data loaded by the completed load instruction that is stored in the storage location.

    CONTROL FLOW GUIDED LOCK ADDRESS PREFETCH AND FILTERING
    10.
    发明申请
    CONTROL FLOW GUIDED LOCK ADDRESS PREFETCH AND FILTERING 审中-公开

    公开(公告)号：US20200151100A1

    公开(公告)日：2020-05-14

    申请号：US16190111

    申请日：2018-11-13

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Susumu Mashimo ,  John Kalamatianos

    IPC: G06F12/0862

    Abstract: A method of prefetching target data includes, in response to detecting a lock-prefixed instruction for execution in a processor, determining a predicted target memory location for the lock-prefixed instruction based on control flow information associating the lock-prefixed instruction with the predicted target memory location. Target data is prefetched from the predicted target memory location to a cache coupled with the processor, and after completion of the prefetching, the lock-prefixed instruction is executed in the processor using the prefetched target data.

Patent Agency Ranking