公开(公告)号：US20190310845A1

公开(公告)日：2019-10-10

申请号：US16450897

申请日：2019-06-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Krishnan V. Ramani ,  Kai Troester ,  Frank C. Galloway ,  David N. Suggs ,  Michael D. Achenbach ,  Betty Ann McDaniel ,  Marius Evers

IPC: G06F9/28 ,  G06F9/30

Abstract: A system and method for tracking stores and loads to reduce load latency when forming the same memory address by bypassing a load store unit within an execution unit is disclosed. Store-load pairs which have a strong history of store-to-load forwarding are identified. Once identified, the load is memory renamed to the register stored by the store. The memory dependency predictor may also be used to detect loads that are dependent on a store but cannot be renamed. In such a configuration, the dependence is signaled to the load store unit and the load store unit uses the information to issue the load after the identified store has its physical address.

公开(公告)号：US11048506B2

公开(公告)日：2021-06-29

申请号：US16450897

申请日：2019-06-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Krishnan V. Ramani ,  Kai Troester ,  Frank C. Galloway ,  David N. Suggs ,  Michael D. Achenbach ,  Betty Ann McDaniel ,  Marius Evers

IPC: G06F9/28 ,  G06F9/30 ,  G06F9/38

Abstract: A system and method for tracking stores and loads to reduce load latency when forming the same memory address by bypassing a load store unit within an execution unit is disclosed. Store-load pairs which have a strong history of store-to-load forwarding are identified. Once identified, the load is memory renamed to the register stored by the store. The memory dependency predictor may also be used to detect loads that are dependent on a store but cannot be renamed. In such a configuration, the dependence is signaled to the load store unit and the load store unit uses the information to issue the load after the identified store has its physical address.

公开(公告)号：US10331357B2

公开(公告)日：2019-06-25

申请号：US15380778

申请日：2016-12-15

Applicant: Advanced Micro Devices, Inc.

Inventor： Betty Ann McDaniel ,  Michael D. Achenbach ,  David N. Suggs ,  Frank C. Galloway ,  Kai Troester ,  Krishnan V. Ramani

IPC: G06F3/06 ,  G06F12/0871 ,  G06F12/0897 ,  G06F9/30

Abstract: A system and method for tracking stores and loads to reduce load latency when forming the same memory address by bypassing a load store unit within an execution unit is disclosed. The system and method include storing data in one or more memory dependent architectural register numbers (MdArns), allocating the one or more MdArns to a MEMFILE, writing the allocated one or more MdArns to a map file, wherein the map file contains a MdArn map to enable subsequent access to an entry in the MEMFILE, upon receipt of a load request, checking a base, an index, a displacement and a match/hit via the map file to identify an entry in the MEMFILE and an associated store, and on a hit, providing the entry responsive to the load request from the one or more MdArns.

公开(公告)号：US20180052613A1

公开(公告)日：2018-02-22

申请号：US15380778

申请日：2016-12-15

Applicant: Advanced Micro Devices, Inc.

Inventor： Betty Ann McDaniel ,  Michael D. Achenbach ,  David N. Suggs ,  Frank C. Galloway ,  Kai Troester ,  Krishnan V. Ramani

IPC: G06F3/06 ,  G06F12/0871 ,  G06F12/0897

CPC classification number: G06F3/0611 ,  G06F3/0631 ,  G06F3/0643 ,  G06F3/0659 ,  G06F3/0673 ,  G06F9/30 ,  G06F12/0871 ,  G06F12/0897 ,  G06F2212/1024 ,  G06F2212/304 ,  G06F2212/463 ,  G06F2212/604

Abstract: A system and method for tracking stores and loads to reduce load latency when forming the same memory address by bypassing a load store unit within an execution unit is disclosed. The system and method include storing data in one or more memory dependent architectural register numbers (MdArns), allocating the one or more MdArns to a MEMFILE, writing the allocated one or more MdArns to a map file, wherein the map file contains a MdArn map to enable subsequent access to an entry in the MEMFILE, upon receipt of a load request, checking a base, an index, a displacement and a match/hit via the map file to identify an entry in the MEMFILE and an associated store, and on a hit, providing the entry responsive to the load request from the one or more MdArns.