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    SECURE VIRTUALIZED PERFORMANCE MONITORING COUNTERS
    1.
    发明公开
    SECURE VIRTUALIZED PERFORMANCE MONITORING COUNTERS 审中-公开

    公开(公告)号：US20240220603A1

    公开(公告)日：2024-07-04

    申请号：US18090831

    申请日：2022-12-29

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： David Kaplan ,  Ruchir Dalal

    IPC: G06F21/53

    CPC classification number: G06F21/53 ,  G06F2221/034

    Abstract: A processing system includes a memory configured to store encrypted information representing state and control information for a guest virtual machine. The processing system further includes a processor configured to selectively reserve exclusive use of a set of performance monitoring counters by the guest virtual machine during execution of the guest virtual machine based on a state of a first control field accessed from the encrypted information for the guest virtual machine. The processor further is configured to permit or deny use of the set of performance monitoring counters by the guest virtual machine based on a state of a second control field set by a hypervisor and accessed from the decryption of the encrypted information for the guest virtual machine accessed from the memory.

    HARDWARE SUPERVISION OF PAGE TABLES
    4.
    发明申请
    HARDWARE SUPERVISION OF PAGE TABLES 审中-公开

    公开(公告)号：US20180081830A1

    公开(公告)日：2018-03-22

    申请号：US15270708

    申请日：2016-09-20

    Applicant: Advanced Micro Devices, Inc.

    Inventor： David Kaplan ,  Sebastien Nussbaum

    IPC: G06F12/14 ,  G06F12/1009

    CPC classification number: G06F12/1483 ,  G06F12/1009 ,  G06F2212/1052

    Abstract: A processing system includes one or more processing units, a memory including a protected region, and a hardware security module. The hardware security module is configured to selectively modify a page table stored in the protected region of the memory in response to write or modify requests from the at least one processing unit. In some variations, the hardware security module can modify the page table in response to verifying that a security criterion is met by the requested modification of the page table. The hardware security module can also access a code signature in response to a request to mark a page in the page table as eligible for execution and selectively mark the page as executable based on whether the code signature matches a signature of code stored in the page.

    Hypervisor secure event handling at a processor
    8.
    发明授权
    Hypervisor secure event handling at a processor 有权

    公开(公告)号：US11842227B2

    公开(公告)日：2023-12-12

    申请号：US16712190

    申请日：2019-12-12

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： David Kaplan ,  Jelena Ilic

    IPC: G06F9/54 ,  G06F9/455 ,  G06F21/55 ,  G06F21/53

    CPC classification number: G06F9/542 ,  G06F9/45533 ,  G06F9/45558 ,  G06F21/554 ,  G06F21/53 ,  G06F2009/45583 ,  G06F2009/45587 ,  G06F2221/033

    Abstract: A virtualized computing environment is protected from a malicious hypervisor by restricting the hypervisor's access to one or more portions of an event (interrupt or exception) handling pathway of a guest virtual machine, wherein the guest virtual machine includes both a secure layer to manage security for the guest and one or more non-secure layers to handle event processing. The hypervisor is restricted from providing normal exception information to the guest virtual machine (referred to simply as a “guest” herein), and instead is only permitted to provide an event signal to the secure layer of the guest. In response to the event signal, the secure layer of the guest accesses a specified region of memory for the event information, reviews the information, and provides the information to another, non-secure, layer of the guest for processing only if the event information complies with specified security protocols.

    Performing store-to-load forwarding of a return address for a return instruction
    9.
    发明授权
    Performing store-to-load forwarding of a return address for a return instruction 有权

    公开(公告)号：US11822923B1

    公开(公告)日：2023-11-21

    申请号：US16451783

    申请日：2019-06-25

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： David Kaplan

    IPC: G06F9/38

    CPC classification number: G06F9/3834 ,  G06F9/3842 ,  G06F9/3861

    Abstract: A load/store unit includes a first queue including a first entry for a store operation and a second queue including a second entry for a load operation that includes a return instruction that redirects a program flow to a location indicated by the return instruction. The load/store unit also includes a processor to determine that the store operation matches the load operation and selectively perform store-to-load forwarding (STLF) of a return address for the return instruction from the first entry to the second entry based on whether the store operation is associated with a call instruction. The load/store unit forwards the return address to the second entry in response to the store operation being associated with the call instruction. The load/store unit blocks forwarding until the store operation retires in response to the store operation not being associated with the call instruction.

    Protection against branch target buffer poisoning by a management layer
    10.
    发明授权
    Protection against branch target buffer poisoning by a management layer 有权

    公开(公告)号：US11797665B1

    公开(公告)日：2023-10-24

    申请号：US16454690

    申请日：2019-06-27

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： David Kaplan ,  Marius Evers

    IPC: G06F9/455 ,  G06F21/53 ,  G06F21/74 ,  G06F9/38

    CPC classification number: G06F21/53 ,  G06F9/45558 ,  G06F21/74 ,  G06F9/3806 ,  G06F2009/45587 ,  G06F2221/033

    Abstract: A processing system includes a branch prediction structure storing information used to predict the outcome of a branch instruction. The processing system also includes a register storing a first identifier of a first process in response to the processing system changing from a first mode that allows the first process to modify the branch prediction structure to a second mode in which the branch prediction structure is not modifiable. The processing system further includes a processor core that selectively flushes the branch prediction structure based on a comparison of a second identifier of a second process and the first identifier stored in the register. The comparison is performed in response to the second process causing a change from the second mode to the first mode.

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