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    Monitoring of memory page transitions between a hypervisor and a virtual machine
    4.
    发明授权
    Monitoring of memory page transitions between a hypervisor and a virtual machine 审中-公开

    公开(公告)号：US10671422B2

    公开(公告)日：2020-06-02

    申请号：US15685861

    申请日：2017-08-24

    Applicant: Advanced Micro Devices, Inc.

    Inventor： David Kaplan ,  Jeremy W. Powell ,  Richard Relph

    IPC: G06F9/455

    Abstract: A security module in a memory access path of a processor of a processing system protects secure information by verifying the contents of memory pages as they transition between one or more virtual machines (VMs) executing at the processor and a hypervisor that provides an interface between the VMs and the processing system's hardware. The security module of the processor is employed to monitor memory pages as they transition between one or more VMs and a hypervisor so that memory pages that have been altered by a hypervisor or other VM cannot be returned to the VM from which they were transitioned.

    Controlling access to pages in a memory in a computing device
    6.
    发明授权
    Controlling access to pages in a memory in a computing device 有权

    公开(公告)号：US10169244B2

    公开(公告)日：2019-01-01

    申请号：US15224302

    申请日：2016-07-29

    Applicant: Advanced Micro Devices, Inc.

    Inventor： David A. Kaplan ,  Jeremy W. Powell ,  Thomas R. Woller

    IPC: G06F12/10 ,  G06F12/1027 ,  G06F12/1009 ,  G06F9/455

    Abstract: The described embodiments perform a method for handling memory accesses by virtual machines in a computing device. The described embodiments include a reverse map table (RMT) and a separate guest accessed pages table (GAPT) for each virtual machine. The RMT has a plurality of entries, each entry including information for identifying a virtual machine that is permitted to access an associated page of data in a memory. Each GAPT has a record of pages being accessed by a corresponding virtual machine. During operation, a table walker receives a request from a given virtual machine to translate a guest physical address to a system physical address. The table walker checks at least one of the RMT and a corresponding GAPT to determine whether the given virtual machine has access to a corresponding page. If not, the table walker terminates the translating. Otherwise, the table walker completes the translating.

    KEY MANAGEMENT FOR SECURE MEMORY ADDRESS SPACES
    7.
    发明申请
    KEY MANAGEMENT FOR SECURE MEMORY ADDRESS SPACES 审中-公开

    公开(公告)号：US20170277898A1

    公开(公告)日：2017-09-28

    申请号：US15081126

    申请日：2016-03-25

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Jeremy W. Powell ,  David A. Kaplan ,  Jesse D. Larrew ,  Thomas R. Woller ,  Joshua Schiffman

    IPC: G06F21/60 ,  G06F21/62

    CPC classification number: G06F21/602 ,  G06F21/53 ,  G06F21/6209 ,  G06F21/6218

    Abstract: A processor employs a security module to manage authentication and encryption keys for the processor. The security module can authenticate itself to other processing systems, such as processing systems providing software to be executed at the processor, can generate keys for encrypting address spaces for the provided software, and can securely import and export information at the encrypted address spaces to and from the processing system. By using a security module that is separate from the processor cores of the processor to perform these security operations, the processing system allows software executing on the processor cores to manage operations based on the authentication and encryption keys without being able to read the keys themselves, thereby preventing unauthorized access by malicious software to the keys.

    Controlling access to pages in a memory in a computing device
    10.
    发明授权
    Controlling access to pages in a memory in a computing device 有权

    公开(公告)号：US10585805B2

    公开(公告)日：2020-03-10

    申请号：US15907593

    申请日：2018-02-28

    Applicant: Advanced Micro Devices, Inc.

    Inventor： David A. Kaplan ,  Jeremy W. Powell ,  Thomas R. Woller

    IPC: G06F12/10 ,  G06F12/1009 ,  G06F9/455

    Abstract: A computing device that handles address translations is described. The computing device includes a hardware table walker and a memory that stores a reverse map table and a plurality of pages of memory. The table walker is configured to use validated indicators in entries in the reverse map table to determine if page accesses are made to pages for which entries are validated. The table walker is further configured to use virtual machine permissions levels information in entries in the reverse map table determine if page accesses for specified operation types are permitted.

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