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    NETWORK INTERFACE WITH LOGGING
    1.
    发明申请
    NETWORK INTERFACE WITH LOGGING 有权
    网络界面与登录

    公开(公告)号：US20140173154A1

    公开(公告)日：2014-06-19

    申请号：US13716357

    申请日：2012-12-17

    Applicant: ADESTO TECHNOLOGIES CORPORATION

    Inventor： Ravi Sunkavalli ,  Malcolm Wing

    IPC: G06F13/40

    CPC classification number: G11C13/0011 ,  G06F13/4027 ,  G06F13/4068 ,  G06F15/177

    Abstract: Structures and methods for improving logging in network structures are disclosed herein. In one embodiment, an apparatus can include: (i) a network interface card (NIC) configured to receive data, to transmit data, and to send data for logging; (ii) a memory log coupled to the NIC, where the memory log comprises non-volatile memory (NVM) configured to write the data sent for logging from the NIC; and (iii) where the data being sent for logging by the memory log occurs substantially simultaneously with the data being received by the NIC, and the data being transmitted from the NIC.

    Abstract translation: 本文公开了用于改善网络结构记录的结构和方法。 在一个实施例中，设备可以包括：（i）网络接口卡（NIC），被配置为接收数据，传输数据和发送用于记录的数据; （ii）耦合到所述NIC的存储器日志，其中所述存储器日志包括被配置为写入从所述NIC发送来记录的数据的非易失性存储器（NVM） 和（iii）其中由存储器日志发送用于记录的数据基本上与由NIC接收的数据同时发生，并且数据从NIC发送。

    System architectures with data transfer paths between different memory types
    2.
    发明授权
    System architectures with data transfer paths between different memory types 有权
    具有不同存储器类型之间的数据传输路径的系统架构

    公开(公告)号：US09455036B1

    公开(公告)日：2016-09-27

    申请号：US14868363

    申请日：2015-09-28

    Applicant: Adesto Technologies Corporation

    Inventor： Ed McKernan ,  Malcolm Wing ,  Ravi Sunkavalli

    IPC: G11C11/34 ,  G11C14/00 ,  G11C13/00 ,  G11C11/408

    CPC classification number: G11C14/0045 ,  G11C11/005 ,  G11C11/401 ,  G11C11/408 ,  G11C11/409 ,  G11C11/4096 ,  G11C13/0011 ,  G11C13/0023 ,  G11C13/0069 ,  G11C14/00

    Abstract: A system can include a first memory section comprising a plurality of volatile memory cells; a second memory section comprising a plurality of nonvolatile memory cells; a first data path configured to transfer data between the first and second memory sections; an interface circuit coupled to receive access commands and address values, the interface circuit configured to determine if a data transfer operation is occurring in the device, and if the data transfer operation is occurring, accessing the address in the first memory section or accessing a location in the second memory section based on a select value, and if the data transfer operation is not occurring, accessing the address in the first memory section; and a compare circuit configured to compare a received address to a predetermined value to generate the select value.

    Abstract translation: 系统可以包括包括多个易失性存储器单元的第一存储器部分; 第二存储器部分，包括多个非易失性存储器单元; 第一数据路径，被配置为在所述第一和第二存储器部分之间传送数据; 接口电路，其被接收以接收访问命令和地址值，所述接口电路被配置为确定所述设备中是否正在发生数据传送操作，并且如果所述数据传送操作正在发生，则访问所述第一存储器部分中的地址或访问位置 在第二存储器部分中基于选择值，并且如果没有发生数据传送操作，则访问第一存储器部分中的地址; 以及比较电路，被配置为将接收到的地址与预定值进行比较以生成所述选择值。

    Network interface with logging
    5.
    发明授权
    Network interface with logging 有权
    具有日志记录的网络接口

    公开(公告)号：US09443584B2

    公开(公告)日：2016-09-13

    申请号：US13716357

    申请日：2012-12-17

    Applicant: ADESTO TECHNOLOGIES CORPORATION

    Inventor： Ravi Sunkavalli ,  Malcolm Wing

    IPC: G06F13/40 ,  G06F11/00 ,  G11C13/00 ,  G06F15/16 ,  G06F15/177

    CPC classification number: G11C13/0011 ,  G06F13/4027 ,  G06F13/4068 ,  G06F15/177

    Abstract: Structures and methods for improving logging in network structures are disclosed herein. In one embodiment, an apparatus can include: (i) a network interface card (NIC) configured to receive data, to transmit data, and to send data for logging; (ii) a memory log coupled to the NIC, where the memory log comprises non-volatile memory (NVM) configured to write the data sent for logging from the NIC; and (iii) where the data being sent for logging by the memory log occurs substantially simultaneously with the data being received by the NIC, and the data being transmitted from the NIC.

    Abstract translation: 本文公开了用于改善网络结构记录的结构和方法。 在一个实施例中，设备可以包括：（i）网络接口卡（NIC），被配置为接收数据，传输数据和发送用于记录的数据; （ii）耦合到所述NIC的存储器日志，其中所述存储器日志包括被配置为写入从所述NIC发送来记录的数据的非易失性存储器（NVM） 和（iii）其中由存储器日志发送用于记录的数据基本上与由NIC接收的数据同时发生，并且数据从NIC发送。

    CODING TECHNIQUES FOR REDUCING WRITE CYCLES FOR MEMORY
    6.
    发明申请
    CODING TECHNIQUES FOR REDUCING WRITE CYCLES FOR MEMORY 有权
    用于减少存储器写入周期的编码技术

    公开(公告)号：US20140149639A1

    公开(公告)日：2014-05-29

    申请号：US13687147

    申请日：2012-11-28

    Applicant: ADESTO TECHNOLOGIES CORPORATION

    Inventor： Ravi Sunkavalli ,  Malcolm Wing

    IPC: G06F12/02

    CPC classification number: G11C16/349 ,  G06F11/1048 ,  G06F12/0238 ,  G11C7/1006 ,  G11C11/5614 ,  G11C11/5628 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0069 ,  G11C16/00 ,  G11C16/3495 ,  G11C2211/5641 ,  G11C2211/5646 ,  G11C2211/5647 ,  G11C2211/5648 ,  H03M13/23

    Abstract: Structures and methods for encoding data to reduce write cycles in a semiconductor memory device are disclosed herein. In one embodiment, a method of writing data to a semiconductor memory device can include: (i) determining a number of significant bits for data to be written in the semiconductor memory device; (ii) determining a tag associated with the data to be written in the semiconductor memory device, where the tag is determined based on the determined number of significant bits; (iii) encoding the data when the tag has a first state, where the tag is configured to indicate data encoding that comprises using N bits of the encoded data to store M bits of the data, where M and N are both positive integers and N is greater than M; and (iv) writing the encoded data and the tag in the semiconductor memory device.

    Abstract translation: 本文公开了用于编码数据以减少半导体存储器件中的写入周期的结构和方法。 在一个实施例中，向半导体存储器件写入数据的方法可以包括：（i）确定要写入半导体存储器件的数据的有效位数; （ii）确定与要写入半导体存储器件的数据相关联的标签，其中基于确定的有效位数量来确定标签; （iii）当标签具有第一状态时对数据进行编码，其中标签被配置为指示数据编码，其包括使用编码数据的N位来存储数据的M位，其中M和N都是正整数，N 大于M; 和（iv）在半导体存储器件中写入编码数据和标签。

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