公开(公告)号：US20250031455A1

公开(公告)日：2025-01-23

申请号：US18908714

申请日：2024-10-07

Applicant: ADVANTEST CORPORATION ,  ISTITUTE OF SCIENCE TOKYO

Inventor： Shinji SUGATANI ,  Takayuki OHBA

IPC: H01L27/06 ,  G11C29/12 ,  H01L21/50 ,  H01L21/66 ,  H01L23/538 ,  H01L25/065

Abstract: When testing a memory chip, the memory chip is determined to be defective if even a portion of the memory chip is defective, and is discarded, which lowers the yield of the three-dimensional memory device. A three-dimensional device is provided comprising a plurality of stacked circuit chips each having one or more circuit blocks in each of a plurality of divided regions obtained by dividing a circuit plane and an interconnect portion communicatively connected, for each group of circuit blocks included in each of the divided regions overlapping in a stacking direction in the plurality of circuit chips, to a predetermined number of circuit blocks sorted from the circuit blocks within the group.

公开(公告)号：US20200061908A1

公开(公告)日：2020-02-27

申请号：US16498398

申请日：2017-04-11

Applicant: ADVANTEST CORPORATION

Inventor： Akio YAMADA ,  Shinji SUGATANI ,  Minoru SOMA

IPC: B29C64/153 ,  B29C64/268 ,  B29C64/393 ,  B29C64/205

Abstract: A 3D additive manufacturing device 100 is provided, including a determination unit 116 that receives modeling data relating to a shape of a section of a 3D structure 66 and determines data of irradiation positions, beam shapes, and irradiation times of a first beam and a second beam along a continuous curve, a storage unit 118 that stores the data determined by the determination unit 116, a deflection control unit 150 that outputs the irradiation position data to a deflector 50 at a timing generated based on the irradiation time data, and a deformation element control unit 130 that outputs the beam shape data to a deformation element 30. Thus, the 3D additive manufacturing device 100 forms a 3D structure by laminating sectional layers constituted by curves in a manner of melting/solidifying a powder layer while performing irradiation with the first beam and the second beam along the continuous curve.

公开(公告)号：US20190118286A1

公开(公告)日：2019-04-25

申请号：US16121581

申请日：2018-09-04

Applicant: ADVANTEST CORPORATION

Inventor： Shinji SUGATANI ,  Shigeki NISHINA ,  Jun MATSUMOTO ,  Masahiro TAKIZAWA ,  Minoru SOMA ,  Akio YAMADA

IPC: B23K15/00 ,  B33Y10/00 ,  B33Y30/00 ,  B33Y50/02 ,  B23K15/02

Abstract: Provided is a three-dimensional laminating and shaping apparatus 100 including a column unit 200 that is configured to output an electron beam EB and deflect the electron beam EB toward the front surface of a powder layer 32, an electron detector 72 that is configured to detect electrons that may be emitted in a predetermined direction from the front surface of the powder layer 32 when the powder layer 32 is irradiated with the electron beam EB, a melting judging unit 410 that is configured to generate a melting signal based on the strength of the detection signal from the electron detector 72, and a deflection controller 420 that is configured to receive the melting signal to determine the condition of the irradiation the electron beam.

公开(公告)号：US20160189930A1

公开(公告)日：2016-06-30

申请号：US14883634

申请日：2015-10-15

Applicant: ADVANTEST CORPORATION

Inventor： Akio YAMADA ,  Shinji SUGATANI ,  Masaki KUROKAWA ,  Masahiro SEYAMA

IPC: H01J37/317

CPC classification number: H01J37/3174 ,  H01J37/045 ,  H01J37/3177 ,  H01J2237/31761 ,  H01J2237/31766 ,  H01J2237/31774

Abstract: To form a complex and fine pattern by combining optical exposure technology and charged particle beam exposure technology, provided is an exposure apparatus that radiates a charged particle beam at a position corresponding to a line pattern on a sample, including a beam generating section that generates a plurality of the charged particle beams at different irradiation positions in a width direction of the line pattern; a scanning control section that performs scanning with the irradiation positions of the charged particle beams along a longitudinal direction of the line pattern; a selecting section that selects at least one charged particle beam to irradiate the sample from among the plurality of charged particle beams, at a designated irradiation position in the longitudinal direction of the line pattern; and an irradiation control section that controls the at least one selected charged particle beam to irradiate the sample.

Abstract translation: 为了通过组合光学曝光技术和带电粒子束曝光技术来形成复杂和精细图案，提供了一种曝光装置，其在与样品上的线图案相对应的位置处辐射带电粒子束，包括生成 在线图案的宽度方向上的不同照射位置处的多个带电粒子束; 扫描控制部，其沿着所述线条图案的长度方向对所述带电粒子束的照射位置进行扫描; 选择部，其选择至少一个带电粒子束，以在所述多个带电粒子束中沿所述线图案的长度方向的指定的照射位置照射所述样本; 以及照射控制部，其控制所述至少一个所选择的带电粒子束照射所述样品。

公开(公告)号：US20240290741A1

公开(公告)日：2024-08-29

申请号：US18481203

申请日：2023-10-04

Applicant: ADVANTEST CORPORATION ,  TOKYO INSTITUTE OF TECHNOLOGY

Inventor： Shinji SUGATANI ,  Masaki TAKAKUWA ,  Shuji UEHARA ,  Takayuki OHBA

IPC: H01L23/00 ,  H01L21/683

CPC classification number: H01L24/32 ,  H01L21/6835 ,  H01L24/27 ,  H01L24/30 ,  H01L24/83 ,  H01L24/97 ,  H01L2221/68363 ,  H01L2224/2732 ,  H01L2224/3003 ,  H01L2224/32225 ,  H01L2224/8384 ,  H01L2224/97 ,  H01L2924/15151

Abstract: A manufacturing method of a semiconductor apparatus in which a semiconductor chip is joined to a target object, the manufacturing method including forming, in a joining region between the semiconductor chip and the target object where the semiconductor chip and the target object should be joined to each other, a plurality of metal paste patterns with a gap being provided in at least a part along a thickness direction between one another, and joining the semiconductor chip and the target object by sintering the plurality of metal paste patterns sandwiched between the semiconductor chip and the target object in a state where the gap exists between one another.

公开(公告)号：US20240234352A9

公开(公告)日：2024-07-11

申请号：US18450435

申请日：2023-08-16

Applicant: ADVANTEST CORPORATION ,  Tokyo Institute of Technology

Inventor： Shinji SUGATANI ,  Takayuki OHBA ,  Norio CHUJO ,  Koji SAKUI ,  Tadashi FUKUDA

IPC: H01L23/00 ,  H01L21/768 ,  H01L23/48 ,  H01L23/522

CPC classification number: H01L24/08 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5226 ,  H01L24/80 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: A stacked chip is provided comprising a first semiconductor chip and a second semiconductor chip, wherein the first semiconductor chip has a first supporting substrate and a first circuit layer including a first region in which a first circuit is formed and a second region in which a second circuit is formed, the second semiconductor chip has a second supporting substrate, a second circuit layer including a third region that corresponds to a position of the first region and a fourth region that corresponds to a position of the second region and in which the second circuit is formed, a first embedded portion embedded in a first hole portion penetrating through the third region and extending to an inside of the second supporting substrate, and a first through via that penetrates through the first embedded portion and the second supporting substrate, and is electrically conducted with the first circuit.

公开(公告)号：US20240136283A1

公开(公告)日：2024-04-25

申请号：US18450420

申请日：2023-08-15

Applicant: ADVANTEST CORPORATION ,  Tokyo Institute of Technology

Inventor： Shinji SUGATANI ,  Takayuki OHBA ,  Koji SAKUI ,  Norio CHUJO

IPC: H01L23/528 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775

CPC classification number: H01L23/528 ,  H01L21/823871 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775

Abstract: To provide a semiconductor apparatus including a transistor element layer having a plurality of transistors which are multi-gate transistors of a floating body structure, a first wiring layer having at least one signal line which electrically connects between a source and a gate or between a drain and a gate of at least one pair of transistors among the plurality of transistors, the first wiring layer being laminated on the side of one surface of the transistor element layer, and a second wiring layer having at least one signal line which electrically connects between a source and a gate or between a drain and a gate of at least another pair of transistors among the plurality of transistors, the second wiring layer being laminated on the side of another surface of the transistor element layer.

公开(公告)号：US20230098533A1

公开(公告)日：2023-03-30

申请号：US17838295

申请日：2022-06-13

Applicant: ADVANTEST CORPORATION ,  Tokyo Institute of Technology

Inventor： Shinji SUGATANI ,  Takayuki OHBA

IPC: H01L25/065 ,  H01L21/768 ,  H01L23/48 ,  H01L23/60

Abstract: Provided is a stacked device comprising: a plurality of circuit layers each having a circuit portion; an insulating layer configured to cover a plurality of circuit portions included in a part of circuit layers of the plurality of circuit layers, and a plurality of conductive vias provided in the insulating layer and electrically connected to the plurality of circuit portions, wherein the conductive via electrically connected to a partial circuit portion of the plurality of circuit portions is electrically insulated on an end surface on an opposite side to the plurality of circuit portions and the partial circuit portion is broken at least partially along a stacking direction.

公开(公告)号：US20240234308A9

公开(公告)日：2024-07-11

申请号：US18450420

申请日：2023-08-16

Applicant: ADVANTEST CORPORATION ,  Tokyo Institute of Technology

Inventor： Shinji SUGATANI ,  Takayuki OHBA ,  Koji SAKUI ,  Norio CHUJO

IPC: H01L23/528 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775

CPC classification number: H01L23/528 ,  H01L21/823871 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775

Abstract: To provide a semiconductor apparatus including a transistor element layer having a plurality of transistors which are multi-gate transistors of a floating body structure, a first wiring layer having at least one signal line which electrically connects between a source and a gate or between a drain and a gate of at least one pair of transistors among the plurality of transistors, the first wiring layer being laminated on the side of one surface of the transistor element layer, and a second wiring layer having at least one signal line which electrically connects between a source and a gate or between a drain and a gate of at least another pair of transistors among the plurality of transistors, the second wiring layer being laminated on the side of another surface of the transistor element layer.

公开(公告)号：US20240186208A1

公开(公告)日：2024-06-06

申请号：US18470458

申请日：2023-09-20

Applicant: ADVANTEST CORPORATION ,  TOKYO INSTITUTE OF TECHNOLOGY

Inventor： Shinji SUGATANI ,  Takayuki OHBA

IPC: H01L23/367 ,  H01L21/56 ,  H01L23/29 ,  H01L23/31 ,  H01L23/427 ,  H01L23/544 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L23/367 ,  H01L21/56 ,  H01L23/291 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/427 ,  H01L23/544 ,  H01L25/0655 ,  H01L25/50 ,  H01L24/13

Abstract: Provided is a semiconductor device, comprising: a semiconductor chip where a circuit is formed on a side of a first surface of a chip substrate and a transition structure is integrated on a side of a second surface which is opposite to the first surface of the chip substrate, wherein the transition structure is obtained by causing a ratio of a substrate material of a chip substrate body to be less than a ratio of the substrate material on the side of the first surface and adding a thermal conductive material which has a higher thermal conductivity than the substrate material; and a thermal conductor which is joined to the second surface of the semiconductor chip and has a higher thermal conductivity than the substrate material.