公开(公告)号：US20240234308A9

公开(公告)日：2024-07-11

申请号：US18450420

申请日：2023-08-16

Applicant: ADVANTEST CORPORATION ,  Tokyo Institute of Technology

Inventor： Shinji SUGATANI ,  Takayuki OHBA ,  Koji SAKUI ,  Norio CHUJO

IPC: H01L23/528 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775

CPC classification number: H01L23/528 ,  H01L21/823871 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775

Abstract: To provide a semiconductor apparatus including a transistor element layer having a plurality of transistors which are multi-gate transistors of a floating body structure, a first wiring layer having at least one signal line which electrically connects between a source and a gate or between a drain and a gate of at least one pair of transistors among the plurality of transistors, the first wiring layer being laminated on the side of one surface of the transistor element layer, and a second wiring layer having at least one signal line which electrically connects between a source and a gate or between a drain and a gate of at least another pair of transistors among the plurality of transistors, the second wiring layer being laminated on the side of another surface of the transistor element layer.

公开(公告)号：US20240136314A1

公开(公告)日：2024-04-25

申请号：US18450435

申请日：2023-08-15

Applicant: ADVANTEST CORPORATION ,  Tokyo Institute of Technology

Inventor： Shinji SUGATANI ,  Takayuki OHBA ,  Norio CHUJO ,  Koji SAKUI ,  Tadashi FUKUDA

IPC: H01L23/00 ,  H01L21/768 ,  H01L23/48 ,  H01L23/522

CPC classification number: H01L24/08 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5226 ,  H01L24/80 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: A stacked chip is provided comprising a first semiconductor chip and a second semiconductor chip, wherein the first semiconductor chip has a first supporting substrate and a first circuit layer including a first region in which a first circuit is formed and a second region in which a second circuit is formed, the second semiconductor chip has a second supporting substrate, a second circuit layer including a third region that corresponds to a position of the first region and a fourth region that corresponds to a position of the second region and in which the second circuit is formed, a first embedded portion embedded in a first hole portion penetrating through the third region and extending to an inside of the second supporting substrate, and a first through via that penetrates through the first embedded portion and the second supporting substrate, and is electrically conducted with the first circuit.

公开(公告)号：US20240234352A9

公开(公告)日：2024-07-11

申请号：US18450435

申请日：2023-08-16

Applicant: ADVANTEST CORPORATION ,  Tokyo Institute of Technology

Inventor： Shinji SUGATANI ,  Takayuki OHBA ,  Norio CHUJO ,  Koji SAKUI ,  Tadashi FUKUDA

IPC: H01L23/00 ,  H01L21/768 ,  H01L23/48 ,  H01L23/522

CPC classification number: H01L24/08 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5226 ,  H01L24/80 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: A stacked chip is provided comprising a first semiconductor chip and a second semiconductor chip, wherein the first semiconductor chip has a first supporting substrate and a first circuit layer including a first region in which a first circuit is formed and a second region in which a second circuit is formed, the second semiconductor chip has a second supporting substrate, a second circuit layer including a third region that corresponds to a position of the first region and a fourth region that corresponds to a position of the second region and in which the second circuit is formed, a first embedded portion embedded in a first hole portion penetrating through the third region and extending to an inside of the second supporting substrate, and a first through via that penetrates through the first embedded portion and the second supporting substrate, and is electrically conducted with the first circuit.

公开(公告)号：US20240136283A1

公开(公告)日：2024-04-25

申请号：US18450420

申请日：2023-08-15

Applicant: ADVANTEST CORPORATION ,  Tokyo Institute of Technology

Inventor： Shinji SUGATANI ,  Takayuki OHBA ,  Koji SAKUI ,  Norio CHUJO

IPC: H01L23/528 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775

CPC classification number: H01L23/528 ,  H01L21/823871 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775

Abstract: To provide a semiconductor apparatus including a transistor element layer having a plurality of transistors which are multi-gate transistors of a floating body structure, a first wiring layer having at least one signal line which electrically connects between a source and a gate or between a drain and a gate of at least one pair of transistors among the plurality of transistors, the first wiring layer being laminated on the side of one surface of the transistor element layer, and a second wiring layer having at least one signal line which electrically connects between a source and a gate or between a drain and a gate of at least another pair of transistors among the plurality of transistors, the second wiring layer being laminated on the side of another surface of the transistor element layer.