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公开(公告)号：US20240250071A1
公开(公告)日：2024-07-25
申请号：US18379990
申请日：2023-10-13
发明人： Javier A. DeLaCruz , Belgacem Haba , Rajesh Katkar
IPC分类号： H01L25/065 , G06F15/76 , G06F15/78 , H01L23/00 , H01L23/532 , H01L25/18
CPC分类号： H01L25/0657 , G06F15/7825 , H01L23/53204 , H01L24/08 , H01L24/83 , H01L25/18 , G06F2015/763 , H01L2224/08145 , H01L2225/06524 , H01L2924/1433 , H01L2924/1434
摘要： The technology relates to a system on chip (SoC). The SoC may include a plurality of network layers which may assist electrical communications either horizontally or vertically among components from different device layers. In one embodiment, a system on chip (SoC) includes a plurality of network layers, each network layer including one or more routers, and more than one device layers, each of the plurality of network layers respectively bonded to one of the device layers. In another embodiment, a method for forming a system on chip (SoC) includes forming a plurality of network layers in an interconnect, wherein each network layer is bonded to an active surface of a respective device layer in a plurality of device layer.
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公开(公告)号：US11824046B2
公开(公告)日：2023-11-21
申请号：US17583872
申请日：2022-01-25
发明人： Javier A. DeLaCruz , Belgacem Haba , Rajesh Katkar
IPC分类号： H01L25/18 , G06F15/78 , H01L23/532 , H01L25/065 , H01L23/00 , G06F15/76
CPC分类号： H01L25/0657 , G06F15/7825 , H01L23/53204 , H01L24/08 , H01L24/83 , H01L25/18 , G06F2015/763 , H01L2224/08145 , H01L2225/06524 , H01L2924/1433 , H01L2924/1434
摘要： The technology relates to a system on chip (SoC). The SoC may include a plurality of network layers which may assist electrical communications either horizontally or vertically among components from different device layers. In one embodiment, a system on chip (SoC) includes a plurality of network layers, each network layer including one or more routers, and more than one device layers, each of the plurality of network layers respectively bonded to one of the device layers. In another embodiment, a method for forming a system on chip (SoC) includes forming a plurality of network layers in an interconnect, wherein each network layer is bonded to an active surface of a respective device layer in a plurality of device layer.
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公开(公告)号：US11715730B2
公开(公告)日：2023-08-01
申请号：US17327169
申请日：2021-05-21
发明人： Min Tao , Liang Wang , Rajesh Katkar , Cyprian Emeka Uzoh
IPC分类号： H01L25/16 , H01L33/00 , H01L25/10 , H01L27/12 , H01L27/15 , H01L25/18 , H01L21/321 , H01L21/02 , H01L23/00 , H01L33/06 , H01L33/32 , H01L33/44 , H01L33/46 , H01L33/62
CPC分类号： H01L25/167 , H01L21/02118 , H01L21/3212 , H01L24/08 , H01L24/80 , H01L25/105 , H01L25/18 , H01L27/1214 , H01L27/156 , H01L33/007 , H01L33/0093 , H01L33/06 , H01L33/32 , H01L33/44 , H01L33/46 , H01L33/62 , H01L2224/08145 , H01L2224/80013 , H01L2224/80355 , H01L2224/80357 , H01L2933/0016 , H01L2933/0025 , H01L2933/0066
摘要： Direct-bonded LED arrays and applications are provided. An example process fabricates a LED structure that includes coplanar electrical contacts for p-type and n-type semiconductors of the LED structure on a flat bonding interface surface of the LED structure. The coplanar electrical contacts of the flat bonding interface surface are direct-bonded to electrical contacts of a driver circuit for the LED structure. In a wafer-level process, micro-LED structures are fabricated on a first wafer, including coplanar electrical contacts for p-type and n-type semiconductors of the LED structures on the flat bonding interface surfaces of the wafer. At least the coplanar electrical contacts of the flat bonding interface are direct-bonded to electrical contacts of CMOS driver circuits on a second wafer. The process provides a transparent and flexible micro-LED array display, with each micro-LED structure having an illumination area approximately the size of a pixel or a smallest controllable element of an image represented on a high-resolution video display.
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公开(公告)号：US11990382B2
公开(公告)日：2024-05-21
申请号：US17865994
申请日：2022-07-15
发明人： Rajesh Katkar
IPC分类号： H01L23/31 , H01L21/48 , H01L21/56 , H01L21/683 , H01L21/78 , H01L23/00 , H01L23/498 , H01L25/10
CPC分类号： H01L23/3107 , H01L21/4853 , H01L21/561 , H01L21/566 , H01L21/568 , H01L21/6835 , H01L21/78 , H01L23/49811 , H01L24/11 , H01L24/94 , H01L24/97 , H01L25/10 , H01L21/4857 , H01L24/13 , H01L24/16 , H01L24/32 , H01L24/83 , H01L24/92 , H01L25/105 , H01L2221/68327 , H01L2221/68372 , H01L2224/12105 , H01L2224/13024 , H01L2224/13025 , H01L2224/131 , H01L2224/16225 , H01L2224/2919 , H01L2224/32225 , H01L2224/73253 , H01L2224/83005 , H01L2224/92242 , H01L2224/97 , H01L2225/1035 , H01L2225/1041 , H01L2225/1058 , H01L2924/15311 , H01L2924/15321 , H01L2924/181 , H01L2924/19107 , H01L2224/97 , H01L2224/83 , H01L2224/131 , H01L2924/014 , H01L2924/181 , H01L2924/00 , H01L2224/2919 , H01L2924/00014
摘要： A microelectronic assembly having a first side and a second side opposite therefrom is disclosed. The microelectronic assembly may include a microelectronic element having a first face, a second face opposite the first face, a plurality of sidewalls each extending between the first and second faces, and a plurality of element contacts. The microelectronic assembly may also include an encapsulation adjacent the sidewalls of the microelectronic element. The microelectronic assembly may include electrically conductive connector elements each having a first end, a second end remote from the first end, and an edge surface extending between the first and second ends, wherein one of the first end or the second end of each connector element is adjacent the first side of the package. The microelectronic assembly may include a redistribution structure having terminals, the redistribution structure adjacent the second side of the package, the terminals being electrically coupled with the connector elements.
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公开(公告)号：US20240006377A1
公开(公告)日：2024-01-04
申请号：US18467481
申请日：2023-09-14
发明人： Liang Wang , Rajesh Katkar
IPC分类号： H01L25/065 , H01L23/31 , H01L25/00 , H01L21/56 , H01L21/768 , H01L23/00 , H01L25/16 , H01L23/538
CPC分类号： H01L25/0652 , H01L23/3135 , H01L25/50 , H01L21/566 , H01L21/76877 , H01L24/19 , H01L24/24 , H01L24/82 , H01L23/3114 , H01L24/96 , H01L21/568 , H01L25/0655 , H01L25/16 , H01L24/20 , H01L23/5381 , H01L23/5386 , H01L24/32 , H01L24/73 , H01L24/97 , H01L24/05 , H01L2225/06527 , H01L2225/06548 , H01L2225/06562 , H01L2924/14 , H01L2224/821 , H01L2224/24145 , H01L2225/06586 , H01L21/561 , H01L23/3128 , H01L2924/18162 , H01L2224/04105 , H01L2224/12105 , H01L2924/18161 , H01L2224/96 , H01L2224/16145 , H01L2224/92124 , H01L2224/73253 , H01L2224/73209 , H01L24/08 , H01L24/16 , H01L2224/97 , H01L2224/08145 , H01L23/49816
摘要： Apparatuses and methods are described. This apparatus includes a bridge die having first contacts on a die surface being in a molding layer of a reconstituted wafer. The reconstituted wafer has a wafer surface including a layer surface of the molding layer and the die surface. A redistribution layer on the wafer surface includes electrically conductive and dielectric layers to provide conductive routing and conductors. The conductors extend away from the die surface and are respectively coupled to the first contacts at bottom ends thereof. At least second and third IC dies respectively having second contacts on corresponding die surfaces thereof are interconnected to the bridge die and the redistribution layer. A first portion of the second contacts are interconnected to top ends of the conductors opposite the bottom ends thereof in part for alignment of the at least second and third IC dies to the bridge die.
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公开(公告)号：US11830804B2
公开(公告)日：2023-11-28
申请号：US16837948
申请日：2020-04-01
IPC分类号： H01L23/50 , H01L23/367 , H01L21/48 , H01L23/64 , H01L23/49
CPC分类号： H01L23/50 , H01L21/4871 , H01L21/4889 , H01L23/367 , H01L23/49 , H01L23/642
摘要： Techniques are disclosed herein for creating over and under interconnects. Using techniques described herein, over and under interconnects are created on an IC. Instead of creating signaling interconnects and power/ground interconnects on a same side of a chip assembly, the signaling interconnects can be placed on an opposing side of the chip assembly as compared to the power interconnects.
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公开(公告)号：US20230317703A1
公开(公告)日：2023-10-05
申请号：US18206512
申请日：2023-06-06
发明人： Min Tao , Liang Wang , Rajesh Katkar , Cyprian Emeka Uzoh
IPC分类号： H01L25/16 , H01L33/00 , H01L25/10 , H01L27/12 , H01L27/15 , H01L25/18 , H01L21/321 , H01L21/02 , H01L23/00
CPC分类号： H01L25/167 , H01L33/007 , H01L25/105 , H01L27/1214 , H01L27/156 , H01L25/18 , H01L21/3212 , H01L21/02118 , H01L24/80 , H01L24/08 , H01L33/0093 , H01L33/06
摘要： Direct-bonded LED arrays and applications are provided. An example process fabricates a LED structure that includes coplanar electrical contacts for p-type and n-type semiconductors of the LED structure on a flat bonding interface surface of the LED structure. The coplanar electrical contacts of the flat bonding interface surface are direct-bonded to electrical contacts of a driver circuit for the LED structure. In a wafer-level process, micro-LED structures are fabricated on a first wafer, including coplanar electrical contacts for p-type and n-type semiconductors of the LED structures on the flat bonding interface surfaces of the wafer. At least the coplanar electrical contacts of the flat bonding interface are direct-bonded to electrical contacts of CMOS driver circuits on a second wafer. The process provides a transparent and flexible micro-LED array display, with each micro-LED structure having an illumination area approximately the size of a pixel or a smallest controllable element of an image represented on a high-resolution video display.
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公开(公告)号：US20240347443A1
公开(公告)日：2024-10-17
申请号：US18381980
申请日：2023-10-19
IPC分类号： H01L23/50 , H01L21/48 , H01L23/367 , H01L23/49 , H01L23/64
CPC分类号： H01L23/50 , H01L21/4871 , H01L21/4889 , H01L23/367 , H01L23/49 , H01L23/642
摘要： Techniques are disclosed herein for creating over and under interconnects. Using techniques described herein, over and under interconnects are created on an IC. Instead of creating signaling interconnects and power/ground interconnects on a same side of a chip assembly, the signaling interconnects can be placed on an opposing side of the chip assembly as compared to the power interconnects.
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公开(公告)号：US20240178256A1
公开(公告)日：2024-05-30
申请号：US18431716
申请日：2024-02-02
发明人： Rajesh Katkar
IPC分类号： H01L27/146 , H01L21/768 , H01L23/00 , H01L23/48
CPC分类号： H01L27/14634 , H01L21/76898 , H01L23/481 , H01L24/18 , H01L27/14618 , H01L27/14636 , H01L27/1464 , H01L27/14687 , H01L27/1469 , H01L2224/04105 , H01L2224/12105 , H01L2224/18 , H01L2224/19 , H01L2224/32145 , H01L2224/73267 , H01L2924/15153 , H01L2924/16235
摘要： Methods of forming a back side image sensor device, as well as back side image sensor devices formed, are disclosed. In one such a method, an image sensor wafer having a first dielectric layer with a first surface is obtained. A reconstituted wafer having a processor die and a second dielectric layer with a second surface is obtained. The reconstituted wafer and the image sensor wafer are bonded to one another including coupling the first surface of the first dielectric layer and the second surface of the second dielectric layer. In another method, such formation is for a processor die bonded to an image sensor wafer. In yet another method, such formation is for a processor die bonded to an image sensor die.
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公开(公告)号：US11935907B2
公开(公告)日：2024-03-19
申请号：US17353103
申请日：2021-06-21
发明人： Rajesh Katkar
IPC分类号： H01L27/146 , H01L21/768 , H01L23/00 , H01L23/48
CPC分类号： H01L27/14634 , H01L21/76898 , H01L23/481 , H01L24/18 , H01L27/14618 , H01L27/14636 , H01L27/1464 , H01L27/14687 , H01L27/1469 , H01L2224/04105 , H01L2224/12105 , H01L2224/18 , H01L2224/19 , H01L2224/32145 , H01L2224/73267 , H01L2924/15153 , H01L2924/16235
摘要： Methods of forming a back side image sensor device, as well as back side image sensor devices formed, are disclosed. In one such a method, an image sensor wafer having a first dielectric layer with a first surface is obtained. A reconstituted wafer having a processor die and a second dielectric layer with a second surface is obtained. The reconstituted wafer and the image sensor wafer are bonded to one another including coupling the first surface of the first dielectric layer and the second surface of the second dielectric layer. In another method, such formation is for a processor die bonded to an image sensor wafer. In yet another method, such formation is for a processor die bonded to an image sensor die.
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