知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

5 records (took 0.011 seconds)

    LOW POWER TRANSIENT VOLTAGE COLLAPSE APPARATUS AND METHOD FOR A MEMORY CELL
    1.
    发明申请
    LOW POWER TRANSIENT VOLTAGE COLLAPSE APPARATUS AND METHOD FOR A MEMORY CELL 有权
    低功耗瞬态电压放大器和存储器单元的方法

    公开(公告)号：US20140340977A1

    公开(公告)日：2014-11-20

    申请号：US13976403

    申请日：2013-05-16

    Applicant: Eric A. Karl ,  Yong-Gee Ng ,  Cyrille Dray

    Inventor： Eric A. Karl ,  Yong-Gee Ng ,  Cyrille Dray

    IPC: G11C5/14 ,  G11C11/419

    CPC classification number: G11C11/419 ,  G11C5/147 ,  G11C11/413 ,  G11C11/414 ,  G11C11/417

    Abstract: Described is an apparatus for memory write assist which consumes low power during write assist operation. The apparatus comprises: a power supply node; a device operable to adjust voltage on the power supply node; and a feedback unit coupled to the power supply node, the feedback unit to control the device in response to a voltage level of the voltage on the power supply node.

    Abstract translation: 描述了一种在写入辅助操作期间消耗低功率的存储器写入辅助装置。 该装置包括：电源节点; 可操作以调节所述电源节点上的电压的装置; 以及耦合到所述电源节点的反馈单元，所述反馈单元响应于所述电源节点上的电压的电压电平来控制所述装置。

    Method and apparatus for providing high voltage with a low voltage CMOS integrated circuit
    3.
    发明授权
    Method and apparatus for providing high voltage with a low voltage CMOS integrated circuit 失效
    用于提供高电压的低压CMOS集成电路的方法和装置

    公开(公告)号：US5748025A

    公开(公告)日：1998-05-05

    申请号：US623969

    申请日：1996-03-29

    Applicant: Yong-Gee Ng ,  Jeff Greason

    Inventor： Yong-Gee Ng ,  Jeff Greason

    IPC: G11C17/16 ,  G11C17/18 ,  H01L27/088 ,  H03K17/0814 ,  H03K17/10 ,  H03K19/003 ,  H03K19/0175

    CPC classification number: H03K17/08142 ,  G11C17/16 ,  G11C17/18 ,  H01L27/088 ,  H03K17/102 ,  H03K19/00315

    Abstract: A method and an apparatus for providing a high voltage to a node of a low voltage tolerant CMOS integrated circuit process. In one embodiment, a pull up circuit is coupled between a high voltage source and the node and a pull down circuit is coupled between the node and a second voltage. The pull up circuit is configured to pull the voltage at the node to a high voltage while the pull down circuit is configured to the voltage at the node to a lower voltage. The pull down circuit includes a pair of series coupled n-channel transistors coupled between the node and the second voltage. The n-channel transistor connected to the node is a special n-channel transistor with a drain to substrate junction breakdown that is greater than the drain to substrate junction breakdown voltage of other ordinary n-channel transistors in the process. The special n-channel transistor is manufactured in an ordinary state-of-the-art CMOS integrated circuit process without adding any costly process steps.

    Abstract translation: 一种用于向低电压容忍CMOS集成电路处理的节点提供高电压的方法和装置。 在一个实施例中，上拉电路耦合在高电压源和节点之间，并且下拉电路耦合在节点和第二电压之间。 上拉电路被配置为将节点处的电压拉到高电压，同时将下拉电路配置为节点处的电压到较低的电压。 下拉电路包括耦合在节点和第二电压之间的一对串联耦合的n沟道晶体管。 连接到节点的n沟道晶体管是具有漏极到衬底结击穿的特殊的n沟道晶体管，其在该过程中大于其它普通n沟道晶体管的漏极到衬底结击穿电压。 特殊的n沟道晶体管是在普通的最先进的CMOS集成电路工艺中制造的，而不增加任何昂贵的工艺步骤。

Patent Agency Ranking