公开(公告)号：US09236459B2

公开(公告)日：2016-01-12

申请号：US13232975

申请日：2011-09-14

Applicant: Yeh-Ning Jou ,  Shang-Hui Tu ,  Jui-Chun Chang ,  Chen-Wei Wu

Inventor： Yeh-Ning Jou ,  Shang-Hui Tu ,  Jui-Chun Chang ,  Chen-Wei Wu

IPC: H01L29/66 ,  H01L29/739 ,  H01L27/02

CPC classification number: H01L29/7393 ,  H01L27/0259

Abstract: Insulated gate bipolar transistor (IGBT) electrostatic discharge (ESD) protection devices are presented. An IGBT-ESD device includes a semiconductor substrate and patterned insulation regions disposed on the semiconductor substrate defining a first active region and a second active region. A high-V N-well is formed in the first active region of the semiconductor substrate. A P-body doped region is formed in the second active region of the semiconductor substrate, wherein the high-V N-well and the P-body doped region are separated with a predetermined distance exposing the semiconductor substrate. A P+ doped drain region is disposed in the high-V N-well. A P+ diffused region and an N+ doped source region are disposed in the P-body doped region. A gate structure is disposed on the semiconductor substrate with one end adjacent to the N+ doped source region and the other end extending over the insulation region.

Abstract translation: 介绍了绝缘栅双极晶体管（IGBT）静电放电（ESD）保护装置。 IGBT-ESD器件包括半导体衬底和设置在半导体衬底上的图案化绝缘区域，其限定第一有源区域和第二有源区域。 在半导体衬底的第一有源区中形成高V N阱。 在半导体衬底的第二有源区中形成P体掺杂区域，其中高V N阱和P体掺杂区域以暴露半导体衬底的预定距离被分离。 P +掺杂漏区设置在高V N阱中。 P +扩散区域和N +掺杂源极区域设置在P体掺杂区域中。 栅极结构设置在半导体衬底上，其一端与N +掺杂源极区相邻，另一端延伸在绝缘区上。

公开(公告)号：US08278736B2

公开(公告)日：2012-10-02

申请号：US12875217

申请日：2010-09-03

Applicant: Yeh-Ning Jou ,  Chia-Wei Hung ,  Shu-Ling Chang ,  Hwa-Chyi Chiou ,  Yeh-Jen Huang

Inventor： Yeh-Ning Jou ,  Chia-Wei Hung ,  Shu-Ling Chang ,  Hwa-Chyi Chiou ,  Yeh-Jen Huang

IPC: H01L29/739 ,  H01L23/60

CPC classification number: H01L27/0259 ,  H01L27/0274

Abstract: An electrostatic discharge protection device coupled between a first power line and a second power line is provided. A first N-type doped region is formed in a P-type well. A first P-type doped region is formed in the first N-type doped region. A second P-type doped region includes a first portion and a second portion. The first portion of the second P-type doped region is formed in the first N-type doped region. The second portion of the second P-type doped region is formed outside of the first N-type doped region. A second N-type doped region is formed in the first portion of the second P-type doped region. The first P-type doped region, the first N-type doped region, the second P-type doped region and the second N-type doped region constitute an insulated gate bipolar transistor (IGBT).

Abstract translation: 提供耦合在第一电力线和第二电力线之间的静电放电保护装置。 在P型阱中形成第一N型掺杂区。 在第一N型掺杂区域中形成第一P型掺杂区域。 第二P型掺杂区域包括第一部分和第二部分。 第二P型掺杂区的第一部分形成在第一N型掺杂区中。 第二P型掺杂区的第二部分形成在第一N型掺杂区的外部。 在第二P型掺杂区域的第一部分中形成第二N型掺杂区域。 第一P型掺杂区域，第一N型掺杂区域，第二P型掺杂区域和第二N型掺杂区域构成绝缘栅双极晶体管（IGBT）。

公开(公告)号：US20110012204A1

公开(公告)日：2011-01-20

申请号：US12887463

申请日：2010-09-21

Applicant: Yeh-Ning Jou ,  Hwa-Chyi Chiou

Inventor： Yeh-Ning Jou ,  Hwa-Chyi Chiou

IPC: H01L27/092

CPC classification number: H01L27/0266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Trig modulation electrostatic discharge (ESD) protection devices are presented. An ESD protection device includes a semiconductor substrate. A high voltage N-well (HVNW) region is formed in the semiconductor substrate. An NDD region, a first P-body region and a second P-body region are formed in the HVNW region, wherein the first P-body region is separated from the second P-body region with a predetermined distance, and wherein the NDD region is isolated from the first P-body region with an isolation region. An N+ doped source region is disposed in the NDD region. An N+ doped region is disposed in the first P-body region. A P+ doped region is disposed in the second P-body region. A first gate is disposed between the N+ doped region and the isolation region, and a second gate is disposed between the N+ doped region and the P+ doped region.

Abstract translation: 提出了Trig调制静电放电（ESD）保护装置。 ESD保护器件包括半导体衬底。 在半导体衬底中形成高电压N阱（HVNW）区域。 在HVNW区域中形成NDD区域，第一P体区域和第二P体区域，其中，第一P体区域与第二P体区域以预定距离分离，并且其中NDD区域 与具有隔离区域的第一P体区隔离。 N +掺杂源区设置在NDD区中。 N +掺杂区域设置在第一P体区域中。 P +掺杂区域设置在第二P体区域中。 第一栅极设置在N +掺杂区域和隔离区域之间，第二栅极设置在N +掺杂区域和P +掺杂区域之间。

公开(公告)号：US07755143B2

公开(公告)日：2010-07-13

申请号：US12177773

申请日：2008-07-22

Applicant: Yeh-Ning Jou ,  Geeng-Lih Lin

Inventor： Yeh-Ning Jou ,  Geeng-Lih Lin

IPC: H01L23/62

CPC classification number: H01L23/585 ,  H01L23/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device is described. The semiconductor device comprises a protected device in a protected device area of a substrate. An electrostatic discharge power clamp device comprising an outer first guard ring and an inner second guard ring is in a guard ring area of the substrate, enclosing the protected device. The first guard ring comprises a first well region having a first conductive type. A first doped region having the first conductive type and a second doped region having a second conductive type are in the first well region. The second guard ring comprises a second well region having a second conductive type. A third doped region has the second conductive type in the second well region. An input/output device is in a periphery device area, coupled to the electrostatic discharge power clamp device.

Abstract translation: 描述半导体器件。 该半导体器件包括在衬底的受保护器件区域中的受保护器件。 包括外部第一保护环和内部第二保护环的静电放电电力钳装置位于衬底的保护环区域中，包围受保护的器件。 第一保护环包括具有第一导电类型的第一阱区。 具有第一导电类型的第一掺杂区域和具有第二导电类型的第二掺杂区域位于第一阱区域中。 第二保护环包括具有第二导电类型的第二阱区。 第三掺杂区域在第二阱区域中具有第二导电类型。 输入/输出装置在外围装置区域中，耦合到静电放电电力钳装置。

公开(公告)号：US07098522B2

公开(公告)日：2006-08-29

申请号：US10956063

申请日：2004-10-04

Applicant: Geeng-Lih Lin ,  Yeh-Ning Jou ,  Ming-Dou Ker

Inventor： Geeng-Lih Lin ,  Yeh-Ning Jou ,  Ming-Dou Ker

IPC: H01L29/00

CPC classification number: H01L27/0262

Abstract: A high voltage device. A high voltage MOS transistor is applied in the ESD protection device to the structure of which a doped region is added, generating a parasitic semiconductor controlled rectifier (SCR) having a shorter discharge path such that the SCR has faster response enhancing ESD protection.

Abstract translation: 高压设备。 在ESD保护器件中将高电压MOS晶体管施加到其中添加掺杂区域的结构，产生具有更短放电路径的寄生半导体可控整流器（SCR），使得SCR具有更快的响应增强ESD保护。

公开(公告)号：US08643111B1

公开(公告)日：2014-02-04

申请号：US13591861

申请日：2012-08-22

Applicant: Yeh-Ning Jou

Inventor： Yeh-Ning Jou

IPC: H01L29/93

CPC classification number: H01L27/0248 ,  H01L27/0259

Abstract: An electrostatic discharge (ESD) protection device is provided. The ESD protection device includes an epitaxy layer disposed on a semiconductor substrate. An isolation pattern is disposed on the epitaxy layer to define a first active region and a second active region, which are surrounded by a first well region. A gate is disposed on the isolation pattern. A first doped region and a second doped region are disposed in the first active region and the second active region, respectively. A drain doped region is disposed in the first doped region. A source doped region and a first pick-up doped region are disposed in the second doped region. A source contact plug having an extended portion connects to the source doped region. A ratio of an area of the extended portion covering the first pick-up doped region to an area of first pick-up doped region is between zero and one.

Abstract translation: 提供静电放电（ESD）保护装置。 ESD保护器件包括设置在半导体衬底上的外延层。 隔离图案设置在外延层上以限定由第一阱区域包围的第一有源区和第二有源区。 一个门设置在隔离图案上。 第一掺杂区域和第二掺杂区域分别设置在第一有源区域和第二有源区域中。 漏极掺杂区域设置在第一掺杂区域中。 源掺杂区域和第一拾取掺杂区域设置在第二掺杂区域中。 具有延伸部分的源极接触插头连接到源极掺杂区域。 覆盖第一拾取掺杂区域的延伸部分的面积与第一拾取掺杂区域的面积的比率在零和一之间。

公开(公告)号：US20120001225A1

公开(公告)日：2012-01-05

申请号：US13232975

申请日：2011-09-14

Applicant: Yeh-Ning Jou ,  Shang-Hui Tu ,  Jui-Chun Chang ,  Chen-Wei Wu

Inventor： Yeh-Ning Jou ,  Shang-Hui Tu ,  Jui-Chun Chang ,  Chen-Wei Wu

IPC: H01L29/739

CPC classification number: H01L29/7393 ,  H01L27/0259

Abstract: Insulated gate bipolar transistor (IGBT) electrostatic discharge (ESD) protection devices are presented. An IGBT-ESD device includes a semiconductor substrate and patterned insulation regions disposed on the semiconductor substrate defining a first active region and a second active region. A high-V N-well is formed in the first active region of the semiconductor substrate. A P-body doped region is formed in the second active region of the semiconductor substrate, wherein the high-V N-well and the P-body doped region are separated with a predetermined distance exposing the semiconductor substrate. A P+ doped drain region is disposed in the high-V N-well. A P+ diffused region and an N+ doped source region are disposed in the P-body doped region. A gate structure is disposed on the semiconductor substrate with one end adjacent to the N+ doped source region and the other end extending over the insulation region.

Abstract translation: 介绍了绝缘栅双极晶体管（IGBT）静电放电（ESD）保护装置。 IGBT-ESD器件包括半导体衬底和设置在半导体衬底上的图案化绝缘区域，其限定第一有源区域和第二有源区域。 在半导体衬底的第一有源区中形成高V N阱。 在半导体衬底的第二有源区中形成P体掺杂区域，其中高V N阱和P体掺杂区域以暴露半导体衬底的预定距离被分离。 P +掺杂漏区设置在高V N阱中。 P +扩散区域和N +掺杂源极区域设置在P体掺杂区域中。 栅极结构设置在半导体衬底上，其一端与N +掺杂源极区相邻，另一端延伸在绝缘区上。

公开(公告)号：US20050179087A1

公开(公告)日：2005-08-18

申请号：US10977023

申请日：2004-11-01

Applicant: Geeng-Lih Lin ,  Yeh-Ning Jou ,  Ming-Dou Ker

Inventor： Geeng-Lih Lin ,  Yeh-Ning Jou ,  Ming-Dou Ker

IPC: H01L23/62 ,  H01L27/02 ,  H01L29/06 ,  H01L29/08 ,  H01L29/40 ,  H01L29/78

CPC classification number: H01L27/0266 ,  H01L29/0653 ,  H01L29/0882 ,  H01L29/402 ,  H01L29/7835

Abstract: An ESD protection device. The ESD protection device is incorporated with a gap structure in a laterally diffused metal oxide semiconductor (LDMOS) field effect transistor, isolating a doped region and a field oxide region. When a parasitical semiconductor controlled rectifier (SCR) of LDMOS is turned off, ESD current is discharged distributively through several discharge paths, avoiding ESD current focus in a signal narrow discharge path and the danger therefrom.

Abstract translation: ESD保护装置。 ESD保护装置在横向扩散的金属氧化物半导体（LDMOS）场效应晶体管中结合有间隙结构，隔离掺杂区域和场氧化物区域。 当LDMOS的寄生半导体可控整流器（SCR）关闭时，ESD电流通过多个放电路径分布放电，避免信号窄放电路径中的ESD电流聚焦及其危险。

公开(公告)号：US20140054707A1

公开(公告)日：2014-02-27

申请号：US13591861

申请日：2012-08-22

Applicant: Yeh-Ning JOU

Inventor： Yeh-Ning JOU

IPC: H01L23/60

CPC classification number: H01L27/0248 ,  H01L27/0259

Abstract: An electrostatic discharge (ESD) protection device is provided. The ESD protection device includes an epitaxy layer disposed on a semiconductor substrate. An isolation pattern is disposed on the epitaxy layer to define a first active region and a second active region, which are surrounded by a first well region. A gate is disposed on the isolation pattern. A first doped region and a second doped region are disposed in the first active region and the second active region, respectively. A drain doped region is disposed in the first doped region. A source doped region and a first pick-up doped region are disposed in the second doped region. A source contact plug having an extended portion connects to the source doped region. A ratio of an area of the extended portion covering the first pick-up doped region to an area of first pick-up doped region is between zero and one.

Abstract translation: 提供静电放电（ESD）保护装置。 ESD保护器件包括设置在半导体衬底上的外延层。 隔离图案设置在外延层上以限定由第一阱区域包围的第一有源区和第二有源区。 一个门设置在隔离图案上。 第一掺杂区域和第二掺杂区域分别设置在第一有源区域和第二有源区域中。 漏极掺杂区域设置在第一掺杂区域中。 源掺杂区域和第一拾取掺杂区域设置在第二掺杂区域中。 具有延伸部分的源极接触插头连接到源极掺杂区域。 覆盖第一拾取掺杂区域的延伸部分的面积与第一拾取掺杂区域的面积的比率在零和一之间。

公开(公告)号：US08278715B2

公开(公告)日：2012-10-02

申请号：US13019846

申请日：2011-02-02

Applicant: Yeh-Ning Jou ,  Chia-Wei Hung ,  Hwa-Chyi Chiou ,  Yeh-Jen Huang ,  Shu-Ling Chang

Inventor： Yeh-Ning Jou ,  Chia-Wei Hung ,  Hwa-Chyi Chiou ,  Yeh-Jen Huang ,  Shu-Ling Chang

IPC: H01L23/62 ,  H01L29/772

CPC classification number: H01L23/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An ESD protection structure is disclosed. A substrate comprises a first conductive type. A first diffusion region is formed in the substrate. A first doped region is formed in the first diffusion region. A second doped region is formed in the first diffusion region. A third doped region is formed in the substrate. A first isolation region is formed in the substrate, covers a portion of the first diffusion region and is located between the second and the third doped regions. A fourth doped region is formed in the substrate. When the first doped region is coupled to a first power line and the third and the fourth doped regions are coupled to a second power line, an ESD current can be released to the second power line from the first power line. During the release of the ESD current, the second doped region is not electrically connected to the first power line.

Abstract translation: 公开了ESD保护结构。 衬底包括第一导电类型。 在基板中形成第一扩散区。 第一掺杂区形成在第一扩散区中。 在第一扩散区域中形成第二掺杂区域。 在衬底中形成第三掺杂区。 第一隔离区形成在衬底中，覆盖第一扩散区的一部分并位于第二和第三掺杂区之间。 在衬底中形成第四掺杂区。 当第一掺杂区耦合到第一电源线并且第三和第四掺杂区耦合到第二电源线时，ESD电流可以从第一电力线释放到第二电力线。 在释放ESD电流期间，第二掺杂区域不与第一电力线电连接。