公开(公告)号：US20120175727A1

公开(公告)日：2012-07-12

申请号：US12986225

申请日：2011-01-07

Applicant: Geeng-Lih Lin ,  Kwang-Ming Lin ,  Shang-Hui Tu ,  Jui-Chun Chang

Inventor： Geeng-Lih Lin ,  Kwang-Ming Lin ,  Shang-Hui Tu ,  Jui-Chun Chang

IPC: H01L23/48 ,  H01L21/283

CPC classification number: H01L29/417 ,  H01L21/743 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/0684

Abstract: The invention provides a semiconductor device. A buried layer is formed in a substrate. A first deep trench contact structure is formed in the substrate. The first deep trench contact structure comprises a conductor and a liner layer formed on a sidewall of the conductor. A bottom surface of the first deep trench contact structure is in contact with the buried layer.

Abstract translation: 本发明提供一种半导体器件。 在衬底中形成掩埋层。 在衬底中形成第一深沟槽接触结构。 第一深沟槽接触结构包括导体和形成在导体的侧壁上的衬里层。 第一深沟槽接触结构的底表面与埋层接触。

公开(公告)号：US07755143B2

公开(公告)日：2010-07-13

申请号：US12177773

申请日：2008-07-22

Applicant: Yeh-Ning Jou ,  Geeng-Lih Lin

Inventor： Yeh-Ning Jou ,  Geeng-Lih Lin

IPC: H01L23/62

CPC classification number: H01L23/585 ,  H01L23/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device is described. The semiconductor device comprises a protected device in a protected device area of a substrate. An electrostatic discharge power clamp device comprising an outer first guard ring and an inner second guard ring is in a guard ring area of the substrate, enclosing the protected device. The first guard ring comprises a first well region having a first conductive type. A first doped region having the first conductive type and a second doped region having a second conductive type are in the first well region. The second guard ring comprises a second well region having a second conductive type. A third doped region has the second conductive type in the second well region. An input/output device is in a periphery device area, coupled to the electrostatic discharge power clamp device.

Abstract translation: 描述半导体器件。 该半导体器件包括在衬底的受保护器件区域中的受保护器件。 包括外部第一保护环和内部第二保护环的静电放电电力钳装置位于衬底的保护环区域中，包围受保护的器件。 第一保护环包括具有第一导电类型的第一阱区。 具有第一导电类型的第一掺杂区域和具有第二导电类型的第二掺杂区域位于第一阱区域中。 第二保护环包括具有第二导电类型的第二阱区。 第三掺杂区域在第二阱区域中具有第二导电类型。 输入/输出装置在外围装置区域中，耦合到静电放电电力钳装置。

公开(公告)号：US07129546B2

公开(公告)日：2006-10-31

申请号：US10992362

申请日：2004-11-19

Applicant: Ming-Dou Ker ,  Kun-Hsien Lin ,  Geeng-Lih Lin

Inventor： Ming-Dou Ker ,  Kun-Hsien Lin ,  Geeng-Lih Lin

IPC: H01L23/62

CPC classification number: H01L27/0266 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/41725 ,  H01L29/7835

Abstract: An ESD protection device. The ESD protection device has a substrate; a channel region, a source region, and a drain region. The channel region is formed on a predetermined area of a surface of the substrate, the channel region has a first side and a second side. The source region is formed adjacent to the first side. The drain region which has a heavily doped region and a lightly doped region formed below the heavily doped region is formed adjacent to the second side. The width along a longitudinal axis of the heavily doped region has variable length and thus the length between one side of the heavily doped region to the second side has variable length.

Abstract translation: ESD保护装置。 ESD保护装置具有基板; 沟道区，源极区和漏极区。 沟道区形成在基板的表面的预定区域上，沟道区具有第一面和第二面。 源区域与第一侧相邻地形成。 具有重掺杂区域和形成在重掺杂区域下方的轻掺杂区域的漏区形成为与第二侧相邻。 沿着重掺杂区域的纵轴的宽度具有可变长度，因此重掺杂区域的一侧与第二侧之间的长度具有可变长度。

公开(公告)号：US07098522B2

公开(公告)日：2006-08-29

申请号：US10956063

申请日：2004-10-04

Applicant: Geeng-Lih Lin ,  Yeh-Ning Jou ,  Ming-Dou Ker

Inventor： Geeng-Lih Lin ,  Yeh-Ning Jou ,  Ming-Dou Ker

IPC: H01L29/00

CPC classification number: H01L27/0262

Abstract: A high voltage device. A high voltage MOS transistor is applied in the ESD protection device to the structure of which a doped region is added, generating a parasitic semiconductor controlled rectifier (SCR) having a shorter discharge path such that the SCR has faster response enhancing ESD protection.

Abstract translation: 高压设备。 在ESD保护器件中将高电压MOS晶体管施加到其中添加掺杂区域的结构，产生具有更短放电路径的寄生半导体可控整流器（SCR），使得SCR具有更快的响应增强ESD保护。

公开(公告)号：US06274911B1

公开(公告)日：2001-08-14

申请号：US09709588

申请日：2000-11-13

Applicant: Geeng-Lih Lin ,  Ming-Dou Ker

Inventor： Geeng-Lih Lin ,  Ming-Dou Ker

IPC: H01L2362

CPC classification number: H01L29/0847 ,  H01L27/0288 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In this invention a current block is implanted into the drain of a transistor to provide for ESD protection and allow the shrinking of the transistor. The block increases the current path into the semiconductor bulk and increases heat dissipation capability. The current block is created by implanting P+ into a region in an N+ drain, and through the drain into an N-well laying below the drain. A high resistance of the block forces drain current flowing from the channel to the drain contact into the semiconductor bulk. The block is the fill width of the drain spreading out the current from an ESD and forcing current from the channel down into the N-well, under the block, and back up to the drain contact area. The increased path and the spreading of the drain current through the semiconductor bulk enhances heat dissipation, and allows smaller devices and layout area with ESD protection.

Abstract translation: 在本发明中，电流块被注入到晶体管的漏极中以提供ESD保护并允许晶体管的收缩。 该块增加了进入半导体体积的电流路径，并增加了散热能力。 通过将P +注入N +漏极中的区域，并通过漏极进入排水管下方的N阱产生当前块。 块的高电阻迫使从沟道流到漏极触点的电流流入半导体体。 该块是漏极的填充宽度，其从ESD放大电流，并且迫使电流从通道向下进入N阱，在块下方，并返回到漏极接触区域。 通过半导体体积增加的漏极电流的路径和扩展增加了散热，并允许具有ESD保护的较小器件和布局面积。

公开(公告)号：US08125028B2

公开(公告)日：2012-02-28

申请号：US12265580

申请日：2008-11-05

Applicant: Hung-Shern Tsai ,  Geeng-Lih Lin ,  Wen-Jya Liang

Inventor： Hung-Shern Tsai ,  Geeng-Lih Lin ,  Wen-Jya Liang

IPC: H01L29/66

CPC classification number: H01L29/7816 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/7809

Abstract: Semiconductor devices for high voltage application are presented. A high power semiconductor device includes a first type doped semiconductor substrate and a second type doped epitaxial layer deposited thereon. A first type doped body region is disposed in the second type doped epitaxial layer. A heavily doped drain region is formed in the second type doped epitaxial layer and isolated from the first type doped body region with an isolation region and a channel. A second type deep heavily doped region extends from the heavily doped drain region to the semiconductor substrate. A pair of inversed type heavily doped source regions is disposed in the first type doped body region. A gate electrode is disposed overlying the channel with a dielectric layer interposed therebetween. The high power semiconductor device is isolated from the other semiconductor devices with a first type deep heavily doped region.

Abstract translation: 介绍了高压应用的半导体器件。 大功率半导体器件包括第一类掺杂半导体衬底和沉积在其上的第二类掺杂外延层。 第一类掺杂体区设置在第二类型掺杂外延层中。 在第二类型掺杂外延层中形成重掺杂漏极区，并与具有隔离区和沟道的第一类型掺杂体区隔离。 第二种深度重掺杂区域从重掺杂漏极区延伸到半导体衬底。 一对反相型重掺杂源极区域设置在第一掺杂体区域中。 栅电极设置在通道上方，介于其间的电介质层。 高功率半导体器件与具有第一类型深度重掺杂区域的其它半导体器件隔离。

公开(公告)号：US20090261409A1

公开(公告)日：2009-10-22

申请号：US12265580

申请日：2008-11-05

Applicant: Hung-Shern Tsai ,  Geeng-Lih Lin ,  Wen-Jya Liang

Inventor： Hung-Shern Tsai ,  Geeng-Lih Lin ,  Wen-Jya Liang

IPC: H01L29/78

CPC classification number: H01L29/7816 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/7809

Abstract: Semiconductor devices for high voltage application are presented. A high power semiconductor device includes a first type doped semiconductor substrate and a second type doped epitaxial layer deposited thereon. A first type doped body region is disposed in the second type doped epitaxial layer. A heavily doped drain region is formed in the second type doped epitaxial layer and isolated from the first type doped body region with an isolation region and a channel. A second type deep heavily doped region extends from the heavily doped drain region to the semiconductor substrate. A pair of inversed type heavily doped source regions is disposed in the first type doped body region. A gate electrode is disposed overlying the channel with a dielectric layer interposed therebetween. The high power semiconductor device is isolated from the other semiconductor devices with a first type deep heavily doped region.

Abstract translation: 介绍了高压应用的半导体器件。 大功率半导体器件包括第一类掺杂半导体衬底和沉积在其上的第二类掺杂外延层。 第一类掺杂体区设置在第二类型掺杂外延层中。 在第二类型掺杂外延层中形成重掺杂漏极区，并与具有隔离区和沟道的第一类型掺杂体区隔离。 第二种深度重掺杂区域从重掺杂漏极区延伸到半导体衬底。 一对反相型重掺杂源极区域设置在第一掺杂体区域中。 栅电极设置在通道上方，介于其间的电介质层。 高功率半导体器件与具有第一类型深度重掺杂区域的其它半导体器件隔离。

公开(公告)号：US07599160B2

公开(公告)日：2009-10-06

申请号：US11946011

申请日：2007-11-27

Applicant: Yeh-Ning Jou ,  Geeng-Lih Lin

Inventor： Yeh-Ning Jou ,  Geeng-Lih Lin

IPC: H02H9/00 ,  H02H1/00

CPC classification number: H01L27/0248

Abstract: An electrostatic discharge (ESD) protection circuit is provided. A transistor is coupled between a node and a ground, and has a gate coupled to the ground. A diode chain is coupled between the node and a pad, and comprises a plurality of first diodes connected in series, wherein the first diode is coupled in a forward conduction direction from the pad to the node. A second diode is coupled between the node and the pad, and the second diode is coupled in a forward conduction direction from the node to the pad.

Abstract translation: 提供静电放电（ESD）保护电路。 晶体管耦合在节点和地之间，并且具有耦合到地的栅极。 二极管链耦合在节点和焊盘之间，并且包括串联连接的多个第一二极管，其中第一二极管以正向传导方向从焊盘耦合到节点。 第二二极管耦合在节点和焊盘之间，并且第二二极管以从节点到焊盘的正向传导方向耦合。

公开(公告)号：US20090140370A1

公开(公告)日：2009-06-04

申请号：US12177773

申请日：2008-07-22

Applicant: Yeh-Ning Jou ,  Geeng-Lih Lin

Inventor： Yeh-Ning Jou ,  Geeng-Lih Lin

IPC: H01L23/62

CPC classification number: H01L23/585 ,  H01L23/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device is described. The semiconductor device comprises a protected device in a protected device area of a substrate. An electrostatic discharge power clamp device comprising an outer first guard ring and an inner second guard ring is in a guard ring area of the substrate, enclosing the protected device. The first guard ring comprises a first well region having a first conductive type. A first doped region having the first conductive type and a second doped region having a second conductive type are in the first well region. The second guard ring comprises a second well region having a second conductive type. A third doped region has the second conductive type in the second well region. An input/output device is in a periphery device area, coupled to the electrostatic discharge power clamp device.

Abstract translation: 描述半导体器件。 该半导体器件包括在衬底的受保护器件区域中的受保护器件。 包括外部第一保护环和内部第二保护环的静电放电电力钳装置位于衬底的保护环区域中，包围受保护的器件。 第一保护环包括具有第一导电类型的第一阱区。 具有第一导电类型的第一掺杂区域和具有第二导电类型的第二掺杂区域位于第一阱区域中。 第二保护环包括具有第二导电类型的第二阱区。 第三掺杂区域在第二阱区域中具有第二导电类型。 输入/输出装置在外围装置区域中，耦合到静电放电电力钳装置。

公开(公告)号：US20050098795A1

公开(公告)日：2005-05-12

申请号：US10956063

申请日：2004-10-04

Applicant: Geeng-Lih Lin ,  Yeh-Ning Jou ,  Ming-Dou Ker

Inventor： Geeng-Lih Lin ,  Yeh-Ning Jou ,  Ming-Dou Ker

IPC: H01L27/02 ,  H01L29/74 ,  H01L31/062

CPC classification number: H01L27/0262

Abstract: A high voltage device. A high voltage MOS transistor is applied in the ESD protection device to the structure of which a doped region is added, generating a parasitic semiconductor controlled rectifier (SCR) having a shorter discharge path such that the SCR has faster response enhancing ESD protection.

Abstract translation: 高压设备。 在ESD保护器件中将高电压MOS晶体管施加到其中添加掺杂区域的结构，产生具有更短放电路径的寄生半导体可控整流器（SCR），使得SCR具有更快的响应增强ESD保护。