Trig modulation electrostatic discharge (ESD) protection devices
    1.
    发明授权
    Trig modulation electrostatic discharge (ESD) protection devices 有权
    触发调制静电放电(ESD)保护装置

    公开(公告)号:US08008726B2

    公开(公告)日:2011-08-30

    申请号:US12887463

    申请日:2010-09-21

    CPC classification number: H01L27/0266 H01L2924/0002 H01L2924/00

    Abstract: Trig modulation electrostatic discharge (ESD) protection devices are presented. An ESD protection device includes a semiconductor substrate. A high voltage N-well (HVNW) region is formed in the semiconductor substrate. An NDD region, a first P-body region and a second P-body region are formed in the HVNW region, wherein the first P-body region is separated from the second P-body region with a predetermined distance, and wherein the NDD region is isolated from the first P-body region with an isolation region. An N+ doped source region is disposed in the NDD region. An N+ doped region is disposed in the first P-body region. A P+ doped region is disposed in the second P-body region. A first gate is disposed between the N+ doped region and the isolation region, and a second gate is disposed between the N+ doped region and the P+ doped region.

    Abstract translation: 提出了Trig调制静电放电(ESD)保护装置。 ESD保护器件包括半导体衬底。 在半导体衬底中形成高电压N阱(HVNW)区域。 在HVNW区域中形成NDD区域,第一P体区域和第二P体区域,其中,第一P体区域与第二P体区域以预定距离分离,并且其中NDD区域 与具有隔离区域的第一P体区隔离。 N +掺杂源区设置在NDD区中。 N +掺杂区域设置在第一P体区域中。 P +掺杂区域设置在第二P体区域中。 第一栅极设置在N +掺杂区域和隔离区域之间,第二栅极设置在N +掺杂区域和P +掺杂区域之间。

    Trig modulation electrostatic discharge (ESD) protection devices
    2.
    发明授权
    Trig modulation electrostatic discharge (ESD) protection devices 有权
    触发调制静电放电(ESD)保护装置

    公开(公告)号:US07821070B2

    公开(公告)日:2010-10-26

    申请号:US12265603

    申请日:2008-11-05

    CPC classification number: H01L27/0266 H01L2924/0002 H01L2924/00

    Abstract: Trig modulation electrostatic discharge (ESD) protection devices are presented. An ESD protection device includes a semiconductor substrate. A high voltage N-well (HVNW) region is formed in the semiconductor substrate. An NDD region, a first P-body region and a second P-body region are formed in the HVNW region, wherein the first P-body region is separated from the second P-body region with a predetermined distance, and wherein the NDD region is isolated from the first P-body region with an isolation region. An N+ doped source region is disposed in the NDD region. An N+ doped region is disposed in the first P-body region. A P+ doped region is disposed in the second P-body region. A first gate is disposed between the N+ doped region and the isolation region, and a second gate is disposed between the N+ doped region and the P+ doped region.

    Abstract translation: 提出了Trig调制静电放电(ESD)保护装置。 ESD保护器件包括半导体衬底。 在半导体衬底中形成高电压N阱(HVNW)区域。 在HVNW区域中形成NDD区域,第一P体区域和第二P体区域,其中,第一P体区域与第二P体区域以预定距离分离,并且其中NDD区域 与具有隔离区域的第一P体区隔离。 N +掺杂源区设置在NDD区中。 N +掺杂区域设置在第一P体区域中。 P +掺杂区域设置在第二P体区域中。 第一栅极设置在N +掺杂区域和隔离区域之间,第二栅极设置在N +掺杂区域和P +掺杂区域之间。

    Electrostatic discharge protection device
    3.
    发明授权
    Electrostatic discharge protection device 有权
    静电放电保护装置

    公开(公告)号:US08507946B2

    公开(公告)日:2013-08-13

    申请号:US13040415

    申请日:2011-03-04

    CPC classification number: H01L23/62 H01L27/0262 H01L2924/0002 H01L2924/00

    Abstract: An electrostatic discharge (ESD) protection device including a substrate, a first doped region, a second doped region, and a third doped region, a gate and a plurality of contacts is disclosed. The substrate includes a first conductive type. The first doped region is formed in the substrate and includes a second conductive type. The second doped region is formed in the substrate and includes the second conductive type. The third doped region is formed in the substrate, includes the first conductive type and is located between the first and the second doped regions. The gate is formed on the substrate, located between the first and the second doped regions and comprises a first through hole. The contacts pass through the first through hole to contact with the third doped region.

    Abstract translation: 公开了一种包括衬底,第一掺杂区域,第二掺杂区域和第三掺杂区域的静电放电(ESD)保护器件,栅极和多个触点。 基板包括第一导电类型。 第一掺杂区域形成在衬底中并且包括第二导电类型。 第二掺杂区域形成在衬底中并且包括第二导电类型。 第三掺杂区域形成在衬底中,包括第一导电类型并且位于第一和第二掺杂区域之间。 栅极形成在衬底上,位于第一和第二掺杂区之间,并且包括第一通孔。 触点通过第一通孔以与第三掺杂区域接触。

    Electrostatic discharge protection device
    4.
    发明授权
    Electrostatic discharge protection device 有权
    静电放电保护装置

    公开(公告)号:US08278736B2

    公开(公告)日:2012-10-02

    申请号:US12875217

    申请日:2010-09-03

    CPC classification number: H01L27/0259 H01L27/0274

    Abstract: An electrostatic discharge protection device coupled between a first power line and a second power line is provided. A first N-type doped region is formed in a P-type well. A first P-type doped region is formed in the first N-type doped region. A second P-type doped region includes a first portion and a second portion. The first portion of the second P-type doped region is formed in the first N-type doped region. The second portion of the second P-type doped region is formed outside of the first N-type doped region. A second N-type doped region is formed in the first portion of the second P-type doped region. The first P-type doped region, the first N-type doped region, the second P-type doped region and the second N-type doped region constitute an insulated gate bipolar transistor (IGBT).

    Abstract translation: 提供耦合在第一电力线和第二电力线之间的静电放电保护装置。 在P型阱中形成第一N型掺杂区。 在第一N型掺杂区域中形成第一P型掺杂区域。 第二P型掺杂区域包括第一部分和第二部分。 第二P型掺杂区的第一部分形成在第一N型掺杂区中。 第二P型掺杂区的第二部分形成在第一N型掺杂区的外部。 在第二P型掺杂区域的第一部分中形成第二N型掺杂区域。 第一P型掺杂区域,第一N型掺杂区域,第二P型掺杂区域和第二N型掺杂区域构成绝缘栅双极晶体管(IGBT)。

    TRIG MODULATION ELECTROSTATIC DISCHARGE (ESD) PROTECTION DEVICES
    5.
    发明申请
    TRIG MODULATION ELECTROSTATIC DISCHARGE (ESD) PROTECTION DEVICES 有权
    TRIG MODULATION静电放电(ESD)保护装置

    公开(公告)号:US20110012204A1

    公开(公告)日:2011-01-20

    申请号:US12887463

    申请日:2010-09-21

    CPC classification number: H01L27/0266 H01L2924/0002 H01L2924/00

    Abstract: Trig modulation electrostatic discharge (ESD) protection devices are presented. An ESD protection device includes a semiconductor substrate. A high voltage N-well (HVNW) region is formed in the semiconductor substrate. An NDD region, a first P-body region and a second P-body region are formed in the HVNW region, wherein the first P-body region is separated from the second P-body region with a predetermined distance, and wherein the NDD region is isolated from the first P-body region with an isolation region. An N+ doped source region is disposed in the NDD region. An N+ doped region is disposed in the first P-body region. A P+ doped region is disposed in the second P-body region. A first gate is disposed between the N+ doped region and the isolation region, and a second gate is disposed between the N+ doped region and the P+ doped region.

    Abstract translation: 提出了Trig调制静电放电(ESD)保护装置。 ESD保护器件包括半导体衬底。 在半导体衬底中形成高电压N阱(HVNW)区域。 在HVNW区域中形成NDD区域,第一P体区域和第二P体区域,其中,第一P体区域与第二P体区域以预定距离分离,并且其中NDD区域 与具有隔离区域的第一P体区隔离。 N +掺杂源区设置在NDD区中。 N +掺杂区域设置在第一P体区域中。 P +掺杂区域设置在第二P体区域中。 第一栅极设置在N +掺杂区域和隔离区域之间,第二栅极设置在N +掺杂区域和P +掺杂区域之间。

    Electrostatic discharge protection device
    6.
    发明授权
    Electrostatic discharge protection device 有权
    静电放电保护装置

    公开(公告)号:US08278715B2

    公开(公告)日:2012-10-02

    申请号:US13019846

    申请日:2011-02-02

    CPC classification number: H01L23/60 H01L2924/0002 H01L2924/00

    Abstract: An ESD protection structure is disclosed. A substrate comprises a first conductive type. A first diffusion region is formed in the substrate. A first doped region is formed in the first diffusion region. A second doped region is formed in the first diffusion region. A third doped region is formed in the substrate. A first isolation region is formed in the substrate, covers a portion of the first diffusion region and is located between the second and the third doped regions. A fourth doped region is formed in the substrate. When the first doped region is coupled to a first power line and the third and the fourth doped regions are coupled to a second power line, an ESD current can be released to the second power line from the first power line. During the release of the ESD current, the second doped region is not electrically connected to the first power line.

    Abstract translation: 公开了ESD保护结构。 衬底包括第一导电类型。 在基板中形成第一扩散区。 第一掺杂区形成在第一扩散区中。 在第一扩散区域中形成第二掺杂区域。 在衬底中形成第三掺杂区。 第一隔离区形成在衬底中,覆盖第一扩散区的一部分并位于第二和第三掺杂区之间。 在衬底中形成第四掺杂区。 当第一掺杂区耦合到第一电源线并且第三和第四掺杂区耦合到第二电源线时,ESD电流可以从第一电力线释放到第二电力线。 在释放ESD电流期间,第二掺杂区域不与第一电力线电连接。

    ELECTROSTATIC DISCHARGE PROTECTION DEVICE
    7.
    发明申请
    ELECTROSTATIC DISCHARGE PROTECTION DEVICE 有权
    静电放电保护装置

    公开(公告)号:US20120146151A1

    公开(公告)日:2012-06-14

    申请号:US13040415

    申请日:2011-03-04

    CPC classification number: H01L23/62 H01L27/0262 H01L2924/0002 H01L2924/00

    Abstract: An electrostatic discharge (ESD) protection device including a substrate, a first doped region, a second doped region, and a third doped region, a gate and a plurality of contacts is disclosed. The substrate includes a first conductive type. The first doped region is formed in the substrate and includes a second conductive type. The second doped region is formed in the substrate and includes the second conductive type. The third doped region is formed in the substrate, includes the first conductive type and is located between the first and the second doped regions. The gate is formed on the substrate, located between the first and the second doped regions and comprises a first through hole. The contacts pass through the first through hole to contact with the third doped region.

    Abstract translation: 公开了一种包括衬底,第一掺杂区域,第二掺杂区域和第三掺杂区域的静电放电(ESD)保护器件,栅极和多个触点。 基板包括第一导电类型。 第一掺杂区域形成在衬底中并且包括第二导电类型。 第二掺杂区域形成在衬底中并且包括第二导电类型。 第三掺杂区域形成在衬底中,包括第一导电类型并且位于第一和第二掺杂区域之间。 栅极形成在衬底上,位于第一和第二掺杂区之间,并且包括第一通孔。 触点通过第一通孔以与第三掺杂区域接触。

    TRIG MODULATION ELECTROSTATIC DISCHARGE (ESD) PROTECTION DEVICES
    8.
    发明申请
    TRIG MODULATION ELECTROSTATIC DISCHARGE (ESD) PROTECTION DEVICES 有权
    TRIG MODULATION静电放电(ESD)保护装置

    公开(公告)号:US20090261417A1

    公开(公告)日:2009-10-22

    申请号:US12265603

    申请日:2008-11-05

    CPC classification number: H01L27/0266 H01L2924/0002 H01L2924/00

    Abstract: Trig modulation electrostatic discharge (ESD) protection devices are presented. An ESD protection device includes a semiconductor substrate. A high voltage N-well (HVNW) region is formed in the semiconductor substrate. An NDD region, a first P-body region and a second P-body region are formed in the HVNW region, wherein the first P-body region is separated from the second P-body region with a predetermined distance, and wherein the NDD region is isolated from the first P-body region with an isolation region. An N+ doped source region is disposed in the NDD region. An N+ doped region is disposed in the first P-body region. A P+ doped region is disposed in the second P-body region. A first gate is disposed between the N+ doped region and the isolation region, and a second gate is disposed between the N+ doped region and the P+ doped region.

    Abstract translation: 提出了Trig调制静电放电(ESD)保护装置。 ESD保护器件包括半导体衬底。 在半导体衬底中形成高电压N阱(HVNW)区域。 在HVNW区域中形成NDD区域,第一P体区域和第二P体区域,其中,第一P体区域与第二P体区域以预定距离分离,并且其中NDD区域 与具有隔离区域的第一P体区隔离。 N +掺杂源区设置在NDD区中。 N +掺杂区域设置在第一P体区域中。 P +掺杂区域设置在第二P体区域中。 第一栅极设置在N +掺杂区域和隔离区域之间,第二栅极设置在N +掺杂区域和P +掺杂区域之间。

    ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT AND INTEFRATED CIRCUIT UTILIZING THE SAME
    9.
    发明申请
    ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT AND INTEFRATED CIRCUIT UTILIZING THE SAME 审中-公开
    静电放电保护电路和使用它们的内置电路

    公开(公告)号:US20100208398A1

    公开(公告)日:2010-08-19

    申请号:US12371092

    申请日:2009-02-13

    Applicant: Yeh-Ning Jou

    Inventor: Yeh-Ning Jou

    Abstract: An ESD protection circuit coupled between a first power line and a second power line to avoid damage to an integrated circuit by an ESD event is disclosed. The ESD protection circuit includes a detection unit, a trigger unit, and a discharging unit. The detection unit asserts a detection signal when the ESD event occurs. The trigger unit asserts a first trigger signal and a second trigger signal when the detection is asserted. The discharging unit provides a discharge path to release an ESD current caused by the ESD event when the first and the second trigger signals are asserted.

    Abstract translation: 公开了一种ESD保护电路,其耦合在第一电力线和第二电力线之间,以避免ESD事件对集成电路的损坏。 ESD保护电路包括检测单元,触发单元和放电单元。 当ESD事件发生时,检测单元断言检测信号。 当检测被确认时,触发单元断言第一触发信号和第二触发信号。 当第一和第二触发信号被断言时,放电单元提供放电路径以释放由ESD事件引起的ESD电流。

    ELECTROSTATIC DISCHARGE PROTECTION CIRCUITS
    10.
    发明申请
    ELECTROSTATIC DISCHARGE PROTECTION CIRCUITS 有权
    静电放电保护电路

    公开(公告)号:US20090135532A1

    公开(公告)日:2009-05-28

    申请号:US11946011

    申请日:2007-11-27

    CPC classification number: H01L27/0248

    Abstract: An electrostatic discharge (ESD) protection circuit is provided. A transistor is coupled between a node and a ground, and has a gate coupled to the ground. A diode chain is coupled between the node and a pad, and comprises a plurality of first diodes connected in series, wherein the first diode is coupled in a forward conduction direction from the pad to the node. A second diode is coupled between the node and the pad, and the second diode is coupled in a forward conduction direction from the node to the pad.

    Abstract translation: 提供静电放电(ESD)保护电路。 晶体管耦合在节点和地之间,并且具有耦合到地的栅极。 二极管链耦合在节点和焊盘之间,并且包括串联连接的多个第一二极管,其中第一二极管以正向传导方向从焊盘耦合到节点。 第二二极管耦合在节点和焊盘之间,并且第二二极管以从节点到焊盘的正向传导方向耦合。

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