公开(公告)号：US09105623B2

公开(公告)日：2015-08-11

申请号：US13480499

申请日：2012-05-25

申请人： Wen-Tai Chiang ,  Chien-Ting Lin

发明人： Wen-Tai Chiang ,  Chien-Ting Lin

IPC分类号： H01L21/8238 ,  H01L29/49 ,  H01L27/088 ,  H01L21/28 ,  H01L29/66 ,  H01L29/51

CPC分类号： H01L29/4966 ,  H01L21/28088 ,  H01L21/823842 ,  H01L27/088 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6659

摘要： A manufacturing method for semiconductor device having metal gate includes providing a substrate having a first semiconductor device and a second semiconductor device formed thereon, the first semiconductor device having a first gate trench and the second semiconductor device having a second gate trench, forming a first work function metal layer and an etch stop layer in the first gate trench and the second gate trench, forming a metal layer having a material the same with the first work function metal layer in the second gate trench, and forming a filling metal layer in the first gate trench and the second gate trench to form a second work function metal layer in the first gate trench.

摘要翻译： 具有金属栅极的半导体器件的制造方法包括：提供具有第一半导体器件和形成在其上的第二半导体器件的衬底，所述第一半导体器件具有第一栅极沟槽，所述第二半导体器件具有第二栅极沟槽，形成第一工件 在第一栅极沟槽和第二栅极沟槽中形成功能金属层和蚀刻停止层，形成具有与第二栅极沟槽中的第一功函数金属层相同的材料的金属层，并且在第一栅极沟槽和第二栅极沟槽中形成填充金属层 栅极沟槽和第二栅极沟槽，以在第一栅极沟槽中形成第二功函数金属层。

公开(公告)号：US20130313648A1

公开(公告)日：2013-11-28

申请号：US13480499

申请日：2012-05-25

申请人： Wen-Tai Chiang ,  Chien-Ting Lin

发明人： Wen-Tai Chiang ,  Chien-Ting Lin

IPC分类号： H01L21/28 ,  H01L27/088

CPC分类号： H01L29/4966 ,  H01L21/28088 ,  H01L21/823842 ,  H01L27/088 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6659

摘要： A manufacturing method for semiconductor device having metal gate includes providing a substrate having a first semiconductor device and a second semiconductor device formed thereon, the first semiconductor device having a first gate trench and the second semiconductor device having a second gate trench, forming a first work function metal layer and an etch stop layer in the first gate trench and the second gate trench, forming a metal layer having a material the same with the first work function metal layer in the second gate trench, and forming a filling metal layer in the first gate trench and the second gate trench to form a second work function metal layer in the first gate trench.

摘要翻译： 一种具有金属栅极的半导体器件的制造方法，包括提供具有第一半导体器件和形成在其上的第二半导体器件的衬底，所述第一半导体器件具有第一栅极沟槽，所述第二半导体器件具有第二栅极沟槽，形成第一工件 在第一栅极沟槽和第二栅极沟槽中形成功能金属层和蚀刻停止层，形成具有与第二栅极沟槽中的第一功函数金属层相同的材料的金属层，并且在第一栅极沟槽和第二栅极沟槽中形成填充金属层 栅极沟槽和第二栅极沟槽，以在第一栅极沟槽中形成第二功函数金属层。

公开(公告)号：US08470714B1

公开(公告)日：2013-06-25

申请号：US13477079

申请日：2012-05-22

申请人： Shih-Hung Tsai ,  Ssu-I Fu ,  Chien-Liang Lin ,  Ying-Tsung Chen ,  Ted Ming-Lang Guo ,  Chin-Cheng Chien ,  Chien-Ting Lin ,  Wen-Tai Chiang

发明人： Shih-Hung Tsai ,  Ssu-I Fu ,  Chien-Liang Lin ,  Ying-Tsung Chen ,  Ted Ming-Lang Guo ,  Chin-Cheng Chien ,  Chien-Ting Lin ,  Wen-Tai Chiang

IPC分类号： H01L21/311

CPC分类号： H01L29/7854 ,  H01L21/31111 ,  H01L21/31116 ,  H01L29/66795

摘要： A method of forming fin structure in integrated circuit comprising the steps of forming a plurality of fin structures on a substrate, covering an insulating layer on said substrate, performing a planarization process to expose mask layers, performing a wet etching process to etch said insulating layer, thereby exposing a part of the sidewall of said mask layer, removing said mask layer, and performing a dry etching process to remove pad layer and a part of said insulating layer, thereby exposing the top surface and a part of sidewall of said fin structures.

摘要翻译： 一种在集成电路中形成鳍结构的方法，包括以下步骤：在衬底上形成多个翅片结构，覆盖所述衬底上的绝缘层，执行平坦化处理以曝光掩模层，执行湿蚀刻工艺以蚀刻所述绝缘层 从而暴露所述掩模层的侧壁的一部分，去除所述掩模层，并进行干蚀刻工艺以去除衬垫层和所述绝缘层的一部分，从而暴露所述鳍结构的顶表面和侧壁的一部分 。

公开(公告)号：US08669618B2

公开(公告)日：2014-03-11

申请号：US13326342

申请日：2011-12-15

申请人： Ssu-I Fu ,  Wen-Tai Chiang ,  Ying-Tsung Chen ,  Shih-Hung Tsai ,  Chien-Ting Lin ,  Chi-Mao Hsu ,  Chin-Fu Lin

发明人： Ssu-I Fu ,  Wen-Tai Chiang ,  Ying-Tsung Chen ,  Shih-Hung Tsai ,  Chien-Ting Lin ,  Chi-Mao Hsu ,  Chin-Fu Lin

IPC分类号： H01L21/70

CPC分类号： H01L21/28114 ,  H01L21/28088 ,  H01L21/823828 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833

摘要： A manufacturing method for semiconductor device having metal gate includes providing a substrate having a first semiconductor device and a second semiconductor device formed thereon, the first semiconductor device having a first gate trench and the second semiconductor device having a second gate trench; sequentially forming a high dielectric constant (high-k) gate dielectric layer and a multiple metal layer on the substrate; forming a first work function metal layer in the first gate trench; performing a first pull back step to remove a portion of the first work function metal layer from the first gate trench; forming a second work function metal layer in the first gate trench and the second gate trench; and performing a second pull back step to remove a portion of the second work function metal layer from the first gate trench and the second gate trench.

摘要翻译： 具有金属栅极的半导体器件的制造方法包括提供具有第一半导体器件和形成在其上的第二半导体器件的衬底，所述第一半导体器件具有第一栅极沟槽，所述第二半导体器件具有第二栅极沟槽; 在基板上依次形成高介电常数（高k）栅介质层和多金属层; 在所述第一栅极沟槽中形成第一功函数金属层; 执行第一拉回步骤以从所述第一栅极沟槽去除所述第一功函数金属层的一部分; 在第一栅极沟槽和第二栅极沟槽中形成第二功函数金属层; 以及执行第二拉回步骤以从所述第一栅极沟槽和所述第二栅极沟槽去除所述第二功函数金属层的一部分。

公开(公告)号：US08664060B2

公开(公告)日：2014-03-04

申请号：US13367382

申请日：2012-02-07

申请人： An-Chi Liu ,  Chun-Hsien Lin ,  Yu-Cheng Tung ,  Chien-Ting Lin ,  Wen-Tai Chiang ,  Shih-Hung Tsai ,  Ssu-I Fu ,  Ying-Tsung Chen ,  Chih-Wei Chen

发明人： An-Chi Liu ,  Chun-Hsien Lin ,  Yu-Cheng Tung ,  Chien-Ting Lin ,  Wen-Tai Chiang ,  Shih-Hung Tsai ,  Ssu-I Fu ,  Ying-Tsung Chen ,  Chih-Wei Chen

IPC分类号： H01L29/78

CPC分类号： H01L29/7834 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78654

摘要： A semiconductor structure and a method of fabricating the same comprising the steps of providing a substrate, forming at least one fin structure on said substrate, forming a gate covering said fin structure, forming a plurality of epitaxial structures covering said fin structures, performing a gate pullback process to reduce the critical dimension (CD) of said gate and separate said gate and said epitaxial structures, forming lightly doped drains (LDD) in said fin structures, and forming a spacer on said gate and said fin structures.

摘要翻译： 一种半导体结构及其制造方法，包括以下步骤：提供衬底，在所述衬底上形成至少一个鳍结构，形成覆盖所述鳍结构的栅极，形成覆盖所述鳍结构的多个外延结构， 拉回过程以减小所述栅极的临界尺寸（CD）并分离所述栅极和所述外延结构，在所述鳍结构中形成轻掺杂的漏极（LDD），以及在所述栅极和所述鳍结构上形成间隔物。

公开(公告)号：US20090256160A1

公开(公告)日：2009-10-15

申请号：US12101725

申请日：2008-04-11

申请人： Po-Wei Liu ,  Cheng-Tzung Tsai ,  Wen-Tai Chiang

发明人： Po-Wei Liu ,  Cheng-Tzung Tsai ,  Wen-Tai Chiang

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7833 ,  H01L21/26506 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7848

摘要： A method for manufacturing a semiconductor device is provided. A gate structure is formed on a substrate. A first dopant implantation and a first strain atom implantation are performed. Thereafter, spacers are formed on sidewalls of the gate structure. A second dopant implantation and a second strain atom implantation are performed. A solid-phase epitaxy annealing process is performed to form source and drain regions made of a semiconductor compound solid-phase epitaxial layer beside the gate structure.

摘要翻译： 提供一种制造半导体器件的方法。 在基板上形成栅极结构。 执行第一掺杂剂注入和第一应变原子注入。 此后，在栅极结构的侧壁上形成间隔物。 进行第二掺杂剂注入和第二应变原子注入。 进行固相外延退火处理以形成由栅极结构旁边的由半导体化合物固相外延层制成的源区和漏区。

公开(公告)号：US08987096B2

公开(公告)日：2015-03-24

申请号：US13367376

申请日：2012-02-07

申请人： Ying-Tsung Chen ,  Chien-Ting Lin ,  Ssu-I Fu ,  Shih-Hung Tsai ,  Wen-Tai Chiang ,  Chih-Wei Chen ,  Chiu-Hsien Yeh ,  Shao-Wei Wang ,  Kai-Ping Wang

发明人： Ying-Tsung Chen ,  Chien-Ting Lin ,  Ssu-I Fu ,  Shih-Hung Tsai ,  Wen-Tai Chiang ,  Chih-Wei Chen ,  Chiu-Hsien Yeh ,  Shao-Wei Wang ,  Kai-Ping Wang

IPC分类号： H01L21/336 ,  H01L21/28 ,  H01L29/66 ,  H01L29/78 ,  H01L29/51

CPC分类号： H01L29/66477 ,  H01L21/28185 ,  H01L29/51 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/7833

摘要： A semiconductor process includes the following steps. A substrate is provided. An ozone saturated deionized water process is performed to form an oxide layer on the substrate. A dielectric layer is formed on the oxide layer. A post dielectric annealing (PDA) process is performed on the dielectric layer and the oxide layer.

摘要翻译： 半导体工艺包括以下步骤。 提供基板。 进行臭氧饱和去离子水处理以在衬底上形成氧化物层。 在氧化物层上形成介电层。 在电介质层和氧化物层上进行后介电退火（PDA）工艺。

公开(公告)号：US20130302976A1

公开(公告)日：2013-11-14

申请号：US13471128

申请日：2012-05-14

申请人： Shih-Hung Tsai ,  Ssu-I Fu ,  Ying-Tsung Chen ,  Chih-Wei Chen ,  Chien-Ting Lin ,  Wen-Tai Chiang

发明人： Shih-Hung Tsai ,  Ssu-I Fu ,  Ying-Tsung Chen ,  Chih-Wei Chen ,  Chien-Ting Lin ,  Wen-Tai Chiang

IPC分类号： H01L21/283

CPC分类号： H01L29/6681 ,  H01L21/28088 ,  H01L21/28114 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/283 ,  H01L21/76224 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/785

摘要： A method of forming a semiconductor device is provided. A first interfacial material layer is formed by a deposition process on a substrate. A dummy gate material layer is formed on the first interfacial material layer. The dummy gate material layer and the first interfacial material layer are patterned to form a stacked structure. An interlayer dielectric (ILD) layer is formed to cover the stacked structure. A portion of the ILD layer is removed to expose a top of the stacked structure. The stacked structure is removed to form a trench in the ILD layer. A second interfacial layer and a first high-k layer are conformally formed at least on a surface of the trench. A composite metal layer is formed to at least fill up the trench.

摘要翻译： 提供一种形成半导体器件的方法。 通过在衬底上的沉积工艺形成第一界面材料层。 在第一界面材料层上形成虚拟栅极材料层。 将虚拟栅材料层和第一界面材料层图案化以形成堆叠结构。 形成层间电介质（ILD）层以覆盖层叠结构。 去除ILD层的一部分以露出堆叠结构的顶部。 去除层叠结构以在ILD层中形成沟槽。 至少在沟槽的表面上共形地形成第二界面层和第一高k层。 复合金属层形成为至少填充沟槽。

公开(公告)号：US20130241003A1

公开(公告)日：2013-09-19

申请号：US13418367

申请日：2012-03-13

申请人： Chien-Ting Lin ,  Wen-Tai Chiang

发明人： Chien-Ting Lin ,  Wen-Tai Chiang

IPC分类号： H01L27/088 ,  H01L21/28

CPC分类号： H01L21/823842 ,  H01L21/28088 ,  H01L21/823431 ,  H01L21/82345 ,  H01L21/823821 ,  H01L29/517 ,  H01L29/66545

摘要： A fin-shaped field-effect transistor process includes the following steps. A substrate is provided. A first fin-shaped field-effect transistor and a second fin-shaped field-effect transistor are formed on the substrate, wherein the first fin-shaped field-effect transistor includes a first metal layer and the second fin-shaped field-effect transistor includes a second metal layer. A treatment process is performed on the first fin-shaped field-effect transistor to adjust the threshold voltage of the first fin-shaped field-effect transistor. A fin-shaped field-effect transistor formed by said process is also provided.

摘要翻译： 鳍状场效应晶体管工艺包括以下步骤。 提供基板。 第一鳍状场效应晶体管和第二鳍状场效应晶体管形成在基板上，其中第一鳍状场效应晶体管包括第一金属层和第二鳍状场效应晶体管 包括第二金属层。 对第一鳍状场效应晶体管进行处理处理，以调整第一鳍状场效应晶体管的阈值电压。 还提供了通过所述方法形成的鳍状场效应晶体管。

公开(公告)号：US08466502B2

公开(公告)日：2013-06-18

申请号：US13070483

申请日：2011-03-24

申请人： Shih-Hung Tsai ,  Wen-Tai Chiang ,  Chen-Hua Tsai ,  Cheng-Tzung Tsai

发明人： Shih-Hung Tsai ,  Wen-Tai Chiang ,  Chen-Hua Tsai ,  Cheng-Tzung Tsai

IPC分类号： H01L29/80 ,  H01L21/00

CPC分类号： H01L21/823443 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/823864 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7843

摘要： A method for fabricating a metal-gate CMOS device. A substrate having thereon a first region and a second region is provided. A first dummy gate structure and a second dummy gate structure are formed within the first region and the second region respectively. A first LDD is formed on either side of the first dummy gate structure and a second LDD is formed on either side of the second dummy gate structure. A first spacer is formed on a sidewall of the first dummy gate structure and a second spacer is formed on a sidewall of the second dummy gate structure. A first embedded epitaxial layer is then formed in the substrate adjacent to the first dummy gate structure. The first region is masked with a seal layer. Thereafter, a second embedded epitaxial layer is formed in the substrate adjacent to the second dummy gate structure.

摘要翻译： 一种制造金属栅CMOS器件的方法。 提供其上具有第一区域和第二区域的基板。 第一虚拟栅极结构和第二虚拟栅极结构分别形成在第一区域和第二区域内。 第一LDD形成在第一虚拟栅极结构的两侧，第二LDD形成在第二虚拟栅极结构的任一侧上。 第一间隔物形成在第一伪栅极结构的侧壁上，第二间隔物形成在第二虚拟栅极结构的侧壁上。 然后在与第一伪栅极结构相邻的衬底中形成第一嵌入式外延层。 第一区域用密封层掩蔽。 此后，在与第二虚拟栅极结构相邻的衬底中形成第二嵌入式外延层。