公开(公告)号：US09029861B2

公开(公告)日：2015-05-12

申请号：US13809930

申请日：2011-05-20

Applicant: Tetsuo Kikuchi ,  Yoshiharu Kataoka ,  Shinya Tanaka ,  Junya Shimada ,  Chikao Yamasaki

Inventor： Tetsuo Kikuchi ,  Yoshiharu Kataoka ,  Shinya Tanaka ,  Junya Shimada ,  Chikao Yamasaki

IPC: H01L29/10 ,  H01L29/76 ,  H01L31/036 ,  H01L31/112 ,  H01L29/786 ,  H01L27/12 ,  H01L27/02

CPC classification number: H01L29/78696 ,  H01L27/0207 ,  H01L27/12 ,  H01L27/1222 ,  H01L27/1225 ,  H01L29/7869

Abstract: Thin film transistors having a high current drive capability and a suitable threshold voltage are provided. The thin film transistor includes a gate electrode, an insulating layer formed on the gate electrode, a semiconductor layer formed on the insulating layer, and source/drain electrodes formed on the semiconductor layer. The semiconductor layer includes a plurality of regions separated from each other in a longitudinal direction of the source/drain electrodes.

Abstract translation: 提供具有高电流驱动能力和合适阈值电压的薄膜晶体管。 薄膜晶体管包括栅电极，形成在栅电极上的绝缘层，形成在绝缘层上的半导体层以及形成在半导体层上的源/漏电极。 半导体层包括在源极/漏极的纵向彼此分离的多个区域。

公开(公告)号：US08994871B2

公开(公告)日：2015-03-31

申请号：US13552813

申请日：2012-07-19

Applicant: Tetsuo Kikuchi

Inventor： Tetsuo Kikuchi

IPC: H04N5/232 ,  G02B7/28 ,  G02B7/36 ,  G02B7/38 ,  G03B13/36

CPC classification number: G02B7/28 ,  G02B7/36 ,  G02B7/38 ,  G03B13/36 ,  H04N5/232 ,  H04N5/23209 ,  H04N5/23212 ,  H04N5/23261

Abstract: A focus controller includes an evaluation value generating unit and a control unit. An evaluation value generating unit obtains a first evaluation value based on a first signal output from a pixel part of an imaging unit by scanning the pixel part in a first direction and obtains a second evaluation value based on a second signal output from the pixel part by scanning the pixel part in a second direction different from the first direction. When a first movement direction of a focus lens based on the first evaluation value and a second movement direction of a focus lens based on the second evaluation value are in the same direction, the control unit performs an auto focus operation in order to move the focus lens in the movement direction determined as the same direction.

Abstract translation: 焦点控制器包括评估值生成单元和控制单元。 评估值生成单元基于从第一方向扫描像素部分而从成像单元的像素部分输出的第一信号获得第一评估值，并且基于从像素部分输出的第二信号获得第二评估值， 沿与第一方向不同的第二方向扫描像素部分。 当基于第二评估值的基于第一评估值和聚焦透镜的第二移动方向的聚焦透镜的第一移动方向处于相同方向时，控制单元执行自动聚焦操作以便移动焦点 透镜在运动方向确定为相同的方向。

公开(公告)号：US08781059B2

公开(公告)日：2014-07-15

申请号：US13637367

申请日：2011-01-06

Applicant: Tetsuo Kikuchi ,  Shinya Tanaka ,  Junya Shimada ,  Chikao Yamasaki

Inventor： Tetsuo Kikuchi ,  Shinya Tanaka ,  Junya Shimada ,  Chikao Yamasaki

IPC: G11C19/00

CPC classification number: G11C19/184 ,  G09G3/3677 ,  G09G2310/0267 ,  G09G2310/0286 ,  G11C19/28

Abstract: A shift register is formed by connecting unit circuits 11 in multi-stage. One electrode of a capacitor Cap2 in the unit circuit 11 is connected to the gate terminal (node N1) of a transistor T2, and the other connected to a node N2. A compensation circuit composed of transistors T3 to T5 provides a clock signal CKB to the node N2 when the node N1 potential is at low level, and applies a low-level potential to the node N2 when the node N1 potential is at high level. Accordingly, even when the gate potential of the transistor T2 changes with a change in a clock signal CK, a signal that cancels out the change is provided through the capacitor Cap2, stabilizing the gate potential of the transistor T2. Thus, a change in the control terminal potential of an output transistor associated with a change in a clock signal is prevented.

Abstract translation: 通过多级连接单元电路11形成移位寄存器。 单元电路11中的电容器Cap2的一个电极连接到晶体管T2的栅极端子（节点N1），另一个连接到节点N2。 当晶体管T3至T5组成的补偿电路在节点N1电位处于低电平时向节点N2提供时钟信号CKB，并且当节点N1电位处于高电平时向节点N2施加低电平电位。 因此，即使当晶体管T2的栅极电位随着时钟信号CK的变化而变化时，通过电容器Cap2提供抵消变化的信号，从而稳定晶体管T2的栅极电位。 因此，防止与时钟信号的变化相关联的输出晶体管的控制端电位的变化。

公开(公告)号：US08742424B2

公开(公告)日：2014-06-03

申请号：US13511661

申请日：2010-07-09

Applicant: Chikao Yamasaki ,  Tetsuo Kikuchi ,  Shinya Tanaka ,  Junya Shimada

Inventor： Chikao Yamasaki ,  Tetsuo Kikuchi ,  Shinya Tanaka ,  Junya Shimada

IPC: H01L29/04

CPC classification number: H01L27/124 ,  G09G3/3266 ,  G09G3/3677 ,  G09G2300/0408 ,  G09G2310/0286 ,  G11C19/184 ,  G11C19/28 ,  H01L29/41733 ,  H01L29/42384

Abstract: The present invention provides a shift register and a display device, each of which operates stably. The present invention relate to a shift register, comprising a thin-film transistor which includes a source electrode, a drain electrode, and a gate electrode, the thin-film transistor being a bottom gate thin-film transistor which includes a comb-shaped source/drain structure, the gate electrode being provided with at least one of a cut and an opening in at least one of a region overlapping with the source electrode and a region overlapping with the drain electrode.

Abstract translation: 本发明提供了一种移位寄存器和显示装置，每个都能稳定地工作。 本发明涉及一种移位寄存器，包括一个薄膜晶体管，它包括一个源电极，一个漏电极和一个栅电极，该薄膜晶体管是一个底栅薄膜晶体管，它包括一个梳形源 漏极结构，栅电极在与源电极重叠的区域和与漏电极重叠的区域中的至少一个区域中设置有切割开口和开口中的至少一个。

公开(公告)号：US08575620B2

公开(公告)日：2013-11-05

申请号：US13697148

申请日：2011-01-25

Applicant: Chikao Yamasaki ,  Shinya Tanaka ,  Tetsuo Kikuchi ,  Junya Shimada

Inventor： Chikao Yamasaki ,  Shinya Tanaka ,  Tetsuo Kikuchi ,  Junya Shimada

IPC: H01L27/14

CPC classification number: H05K1/18 ,  G02F1/13454 ,  H01L27/1225 ,  H01L27/1251 ,  H05K7/00

Abstract: The present invention provides a circuit board with a reduced circuit area, and a display device comprising the circuit board and a narrower picture frame. The circuit board of the present invention comprises: a bottom gate thin film transistor comprising a first semiconductor layer, a first gate electrode, a first source electrode, and a first drain electrode; and a top gate thin film transistor comprising a second semiconductor layer, a second gate electrode, a second source electrode, and a second drain electrode, wherein the first semiconductor layer and the second semiconductor layer are formed from the same material, and the first drain electrode or the first source electrode and the second gate electrode are connected without interposing any other thin film transistor therebetween, and have the same electric potential.

Abstract translation: 本发明提供一种具有减小电路面积的电路板，以及包括电路板和较窄图像帧的显示装置。 本发明的电路板包括：底栅薄膜晶体管，包括第一半导体层，第一栅电极，第一源电极和第一漏电极; 以及包括第二半导体层，第二栅电极，第二源电极和第二漏电极的顶栅薄膜晶体管，其中所述第一半导体层和所述第二半导体层由相同的材料形成，并且所述第一漏极 电极或第一源电极和第二栅极电极连接而不在其间插入任何其它薄膜晶体管，并且具有相同的电位。

公开(公告)号：US08559588B2

公开(公告)日：2013-10-15

申请号：US13264828

申请日：2009-12-25

Applicant: Tetsuo Kikuchi ,  Shinya Tanaka ,  Chikao Yamasaki ,  Junya Shimada

Inventor： Tetsuo Kikuchi ,  Shinya Tanaka ,  Chikao Yamasaki ,  Junya Shimada

IPC: G11C19/00

CPC classification number: G09G3/20 ,  G09G3/3677 ,  G09G2300/0426 ,  G09G2310/0267 ,  G09G2310/0286 ,  G09G2310/0291 ,  G09G2330/021 ,  G11C19/28

Abstract: Provided is a shift register configured by cascade connecting unit circuits each including a bootstrap circuit. In at least one example embodiment, for the unit circuits, a time period during which a transistor is in an ON state and a clock signal is high level corresponds to a clock passing period. Among transistors whose one conduction terminal is connected to a gate of the transistor, channel lengths of transistors configured such that a low-level potential is fed to gates of the transistors to turn the transistors to an OFF state in the clock passing period and that a low-level potential is applied to the conduction terminal of the transistors in the clock passing period are made longer than the channel length of the transistor. With this, it is possible to reduce a leakage current in the clock passing period, and to prevent the fluctuation of a gate potential of the transistor and dullness in an output signal from occurring.

Abstract translation: 提供一种移位寄存器，其通过级联连接单元电路来构成，每个单元电路包括自举电路。 在至少一个示例性实施例中，对于单元电路，晶体管处于导通状态和时钟信号为高电平的时间段对应于时钟传递周期。 在其一个导通端子连接到晶体管的栅极的晶体管中，晶体管的沟道长度被配置为使得低电平电位被馈送到晶体管的栅极，以在晶体管的时钟通过期间将晶体管转换为截止状态，并且 在晶体管的导通端子中施加低电位电位使晶体管的通过时间长于晶体管的沟道长度。 由此，可以减小时钟通过期间的漏电流，并且防止晶体管的栅极电位的波动和输出信号中的钝度发生。

公开(公告)号：US20130092927A1

公开(公告)日：2013-04-18

申请号：US13639138

申请日：2011-01-17

Applicant: Atsuhito Murai ,  Shinya Tanaka ,  Hideki Kitagawa ,  Hajime Imai ,  Mitsunori Imade ,  Tetsuo Kikuchi ,  Kazunori Morimoto ,  Junya Shimada ,  Jun Nishimura

Inventor： Atsuhito Murai ,  Shinya Tanaka ,  Hideki Kitagawa ,  Hajime Imai ,  Mitsunori Imade ,  Tetsuo Kikuchi ,  Kazunori Morimoto ,  Junya Shimada ,  Jun Nishimura

IPC: H01L27/15

CPC classification number: H01L27/15 ,  G02F1/13318 ,  G02F1/13338 ,  G02F1/136204 ,  G02F1/1368 ,  H01L27/1222 ,  H01L27/1225 ,  H01L27/1251 ,  H01L29/42384 ,  H01L29/78633 ,  H01L29/7869

Abstract: The circuit board (1) of the present invention includes a plurality of transistor elements provided on a single insulating substrate (2) for respective pixels that are two-dimensionally arranged or respective pixels in a group of a predetermined number of the pixels. At least one of the plurality of transistor elements is an oxide TFT (10) having a channel layer (11) formed by an oxide semiconductor, and at least another of the plurality of transistor elements is an a-Si TFT (20) having a channel layer (21) formed by, for example, an amorphous silicon semiconductor. Each of the oxide TFT (10) and the a-Si TFT (20) is a bottom-gate transistor.

Abstract translation: 本发明的电路板（1）包括设置在单个绝缘基板（2）上的多个晶体管元件，用于各个像素的二维排列或者在一组预定数量的像素中的各个像素。 多个晶体管元件中的至少一个是具有由氧化物半导体形成的沟道层（11）的氧化物TFT（10），并且多个晶体管元件中的至少另一个是具有 沟道层（21）由例如非晶硅半导体形成。 氧化物TFT（10）和a-Si TFT（20）中的每一个都是底栅晶体管。

公开(公告)号：US20130026283A1

公开(公告)日：2013-01-31

申请号：US13556589

申请日：2012-07-24

Applicant: Tetsuo Kikuchi ,  Ryoya Shinjo ,  Yuki Igarashi ,  Haruhiko Tanami ,  Ryohei Maruyama ,  Shin Genta ,  Naoki Wakayama

Inventor： Tetsuo Kikuchi ,  Ryoya Shinjo ,  Yuki Igarashi ,  Haruhiko Tanami ,  Ryohei Maruyama ,  Shin Genta ,  Naoki Wakayama

IPC: B65H43/00

CPC classification number: B65H20/005 ,  B65H23/185 ,  B65H2301/512125 ,  B65H2403/942 ,  B65H2404/14 ,  B65H2511/112 ,  B65H2515/32 ,  B65H2701/1311 ,  B65H2801/12 ,  B65H2220/01 ,  B65H2220/02

Abstract: A conveyance apparatus includes: a supply unit rotatably supporting a roll member around which a sheet is wound in form of a roll and configured to supply the sheet from the roll member; a motor for rotating the roll member; a roller pair configured to convey the sheet supplied from the supply unit while pinching the sheet; and a control unit configured to set the torque of the motor according to sheet information related to the sheet when taking up the sheet on the roll member by driving the motor while the sheet is pinched by the roller pair being stopped.

Abstract translation: 一种输送装置，包括：供给单元，其可旋转地支撑辊状构件，片材绕辊卷绕成卷，并且构造成从卷构件供给片材; 用于旋转辊构件的电动机; 辊对，构造成在夹持片材的同时传送从供给单元供给的片材; 以及控制单元，被配置为当通过所述辊对被夹持而停止时，通过驱动所述电动机来将与所述纸张相关的纸张信息设置为与所述纸张相关的纸张信息。

公开(公告)号：US20130021516A1

公开(公告)日：2013-01-24

申请号：US13552813

申请日：2012-07-19

Applicant: Tetsuo Kikuchi

Inventor： Tetsuo Kikuchi

IPC: H04N5/232

CPC classification number: G02B7/28 ,  G02B7/36 ,  G02B7/38 ,  G03B13/36 ,  H04N5/232 ,  H04N5/23209 ,  H04N5/23212 ,  H04N5/23261

Abstract: A focus controller includes an evaluation value generating unit and a control unit. An evaluation value generating unit obtains a first evaluation value based on a first signal output from a pixel part of an imaging unit by scanning the pixel part in a first direction and obtains a second evaluation value based on a second signal output from the pixel part by scanning the pixel part in a second direction different from the first direction. When a first movement direction of a focus lens based on the first evaluation value and a second movement direction of a focus lens based on the second evaluation value are in the same direction, the control unit performs an auto focus operation in order to move the focus lens in the movement direction determined as the same direction.

Abstract translation: 焦点控制器包括评估值生成单元和控制单元。 评估值生成单元基于从第一方向扫描像素部分而从成像单元的像素部分输出的第一信号获得第一评估值，并且基于从像素部分输出的第二信号获得第二评估值， 沿与第一方向不同的第二方向扫描像素部分。 当基于第二评估值的基于第一评估值和聚焦透镜的第二移动方向的聚焦透镜的第一移动方向处于相同方向时，控制单元执行自动聚焦操作以便移动焦点 透镜在运动方向确定为相同的方向。

公开(公告)号：US20120293471A1

公开(公告)日：2012-11-22

申请号：US13521308

申请日：2010-12-01

Applicant: Masahiro Yoshida ,  Isao Ogasawara ,  Satoshi Horiuchi ,  Takaharu Yamada ,  Shinya Tanaka ,  Tetsuo Kikuchi

Inventor： Masahiro Yoshida ,  Isao Ogasawara ,  Satoshi Horiuchi ,  Takaharu Yamada ,  Shinya Tanaka ,  Tetsuo Kikuchi

IPC: G09G3/36 ,  G09G5/00

CPC classification number: G02F1/13454 ,  G02F1/13458 ,  G02F2001/136263 ,  H01L27/124

Abstract: A gate driving circuit (60) separated into a plurality of stages (ST) is provided. In each of the stages (ST), TFT elements (T1) through (T4) are provided, branch lines (78) that connect clock lines (72, 74) to the TFT elements are provided. Junction lines (79A, 79B) are each extended from the branch line (78A) of interest to electrically connect the branch line (78A) of interest to the TFT elements (T2, T4) provided in the stage (ST(j)) different from the stage (ST (j−1)) where the TFT elements (T1, T3) connected to the branch line (78A) of interest are provided.

Abstract translation: 提供分离为多个级（ST）的栅极驱动电路（60）。 在各级（ST）中，设置TFT元件（T1）至（T4），将时钟线（72,74）连接到TFT元件的支线（78）设置。 各接线（79A，79B）各自从感兴趣的支线（78A）延伸，将感兴趣的分支线（78A）电连接到设置在台（ST（j））中的TFT元件（T2，T4）不同 提供与感兴趣的分支线路（78A）连接的TFT元件（T1，T3）的级（ST（j-1））。